Mask plate and processes for manufacturing ultraviolet mask plate and array substrate

Patent metadata

Field	Value
Publication number	US-9329445-B2
Application number	US-201414416784-A
Country	US
Kind code	B2
Filing date	Jun 26, 2014
Priority date	Jun 10, 2014
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

The present disclosure discloses a mask plate and processes for manufacturing an ultraviolet mask plate and an array substrate. The present disclosure relates to the field of display technology and can reduce costs for manufacturing ultraviolent mask plates. The mask plate comprises a transparent area, a semi-transparent area, and a non-transparent area, wherein the transparent area and the non-transparent area correspond to a frame glue area and a layer pattern area of a liquid crystal display panel, respectively, and other regions of the mask plate constitute said semi-transparent area. The present disclosure can be used in the manufacture of display devices of liquid crystal display televisions, liquid crystal displays, mobile phones, tablet computers, etc.

First claim

The invention claimed is:

1. A mask plate, comprising a transparent area, a semi-transparent area, and a non-transparent area, wherein the transparent area and the non-transparent area correspond to a frame glue area and a layer pattern area of a liquid crystal display panel, respectively, and other regions of the mask plate constitute said semi-transparent area.

2. The mask plate of claim 1 , wherein the transmittance of the semi-transparent area ranges from ½ to ⅔.

3. The mask plate of claim 1 , wherein the layer pattern is in the form of a gate metal layer pattern, and a source/drain metal layer pattern and a transparent electrode layer pattern of said liquid crystal display panel are located in the semi-transparent area.

4. The mask plate of claim 1 , wherein the layer pattern is in the form of a source/drain metal layer pattern, and a gate metal layer pattern and a transparent electrode layer pattern of said liquid crystal display panel are located in the semi-transparent area.

5. The mask plate of claim 1 , wherein the layer pattern is in the form of a transparent electrode layer pattern, and a gate metal layer pattern and source/drain metal layer pattern of said liquid crystal display panel are located in said semi-transparent area.

6. A process for manufacturing an ultraviolet mask plate, comprising:
forming a metal layer on a base substrate;
coating a photoresist layer on the metal layer;
exposing said photoresist layer with a first illumination intensity through a mask plate, wherein the mask plate includes a transparent area, a semi-transparent area, and a non-transparent layer, the transparent area and non-transparent area corresponding to a frame glue area and a layer pattern area of a liquid crystal display panel, respectively, and other regions of the mask plate constituting said semi-transparent area;
removing the photoresist layer corresponding to the transparent area of the mask plate;
etching said metal layer; and
removing the remaining photoresist layer.

7. A process for manufacturing an array substrate, comprising:
forming a material layer to be etched on a base substrate;
coating a photoresist layer on the material to be etched;
exposing said photoresist layer with a second illumination intensity through a mask plate, wherein the mask plate includes a transparent area, a semi-transparent area, and a non-transparent layer, the transparent area and non-transparent area corresponding to a frame glue area and a layer pattern area of a liquid crystal display panel, respectively, and other regions of the mask plate constituting said semi-transparent area;
removing the photoresist layer corresponding to the transparent area and semi-transparent area of the mask plate;
etching said material to be etched to form a layer pattern; and
removing the remaining photoresist layer.

8. The process of claim 7 , wherein the material layer to be etched is in the form of a metal layer, and the layer pattern is in the form of a gate metal layer pattern or a source/drain metal layer pattern.

9. The process of claim 7 , wherein the material layer to be etched is in the form of a transparent electrode layer, and the layer pattern is in the form of a transparent electrode layer pattern.

Assignees

• Shenzhen China Star Optoelect

Inventors

• Xu Xiangyang

Classifications

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10D64/013

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• G02F1/1339 Primary

  Gaskets; Spacers; Sealing of cells · CPC title

• G03F1/76

  Patterning of masks by imaging · CPC title