GOA circuit, display device and drive method of GOA circuit

Patent metadata

Field	Value
Publication number	US-9898984-B2
Application number	US-201514888426-A
Country	US
Kind code	B2
Filing date	Sep 29, 2015
Priority date	Sep 23, 2015
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

The invention discloses a GOA circuit, a display device and a drive method of a GOA circuit, the GOA circuit is set to be GOA units including a plurality of levels, a N leveled GOA unit is applied to charge a N leveled scanning line of a display region of the display device, the N leveled scanning line is connected to a first gate all on signal and a second gate all on signal, which can guarantee scanning lines corresponding to all the GOA units are being charged under control of the first gate all on signal and the second gate all on signal. The invention can carry out an all gate on function according to the method above.

First claim

What is claimed is:

1. A GOA circuit, applied to drive a display device, wherein the GOA circuit comprises a plurality of levels of GOA units, a N level of the GOA units is applied to charge a N leveled scanning line of a display region of the display device, the N leveled scanning line is connected to a first gate all on signal and a second gate all on signal, which is applied to guarantee scanning lines corresponding to all the GOA units are being charged under control of the first gate all on signal and the second gate all on signal, where N is a positive integer that is larger than or equal to 1;
wherein the N leveled GOA unit comprises a N leveled pull-up control module, a N leveled pull-up module, a N leveled pull-down module and a N leveled pull-down maintenance module;
an output terminal of the N leveled pull-up control module is connected to a N leveled grid signal location;
an input terminal of the N leveled pull-up module is connected to the N leveled grid signal location, a control terminal of the N leveled pull-up module receives a first clock signal, an output terminal of the N leveled pull-up module is connected to the N leveled scanning line;
an input terminal of the N leveled pull-down module and a N leveled pull-down gate all on signal location are connected, a control terminal of the N leveled pull-down module receives a first voltage signal, an output terminal of a N leveled pull-down module is connected to the N leveled grid signal location and the N leveled scanning line respectively;
a control terminal of the N leveled pull-down maintenance module receives a second clock signal or a third clock signal, an output terminal of the N leveled pull-down maintenance module is connected to the N leveled pull-down gate all on signal location;
wherein the N leveled pull-up control module outputs a pull-up gate all on signal to the N leveled grid signal location, which leads to the pull-up module outputs the first clock signal to the N leveled scanning line responding to the pull-up gate all on signal, after charging the N leveled scanning line responding to the first clock signal, the N leveled pull-down maintenance module outputs the second clock signal or the third clock signal to the N leveled pull-down gate all on signal location, hence the pull-down module transmits the first voltage signal to the N leveled grid signal location and the N leveled scanning line respectively, which can turn off the N leveled scanning line, and the N leveled pull-down maintenance module continues to respond to the second clock signal or the third clock signal and maintain the N leveled scanning line turned off.

2. The GOA circuit according to claim 1 , wherein the N leveled GOA unit comprises a gate all on control module, the gate all on control module comprises a first transistor, a grid of the first transistor receives the first gate all on signal, a source electrode of the first transistor receives the second gate all on signal, a drain electrode of the first transistor and the N leveled scanning line are connected.

3. The GOA circuit according to claim 1 , wherein the N leveled pull-up control module comprises a second transistor, a third transistor and a fourth transistor;
a grid of the second transistor receives a positive scanning signal, a source electrode of the second transistor is connected to a scanning line of a former leveled GOA unit, a drain electrode of the second transistor is connected to a source electrode of the fourth transistor;
a grid of the third transistor receives a negative scanning signal, a source electrode of the third transistor is connected to scanning lines of the later leveled GOA unit, a drain electrode of the third transistor is connected to a source electrode of the fourth transistor;
a grid of the fourth transistor receives a fourth clock signal, a drain electrode of the fourth transistor is connected to the N leveled grid signal location.

4. The GOA circuit according to claim 1 , wherein the N leveled pull-up module comprises a fifth transistor and a first capacitor;
a grid of the fifth transistor is connected to the N leveled grid signal location, a source electrode of the fifth transistor receives the first clock signal, a drain electrode of the fifth transistor is connected to the N leveled scanning line;
one end of the first capacitor is connected to a grid of the fifth transistor, the other end of the capacitor is connected to the N leveled scanning line.

5. The GOA circuit according to claim 1 , wherein the N leveled pull-down module comprises a sixth transistor and a seventh transistor;
a grid of the sixth transistor is connected to the N leveled pull-down gate all on signal location, a source electrode of the sixth transistor receives the first voltage signal, a drain electrode of the sixth transistor is connected to the N leveled grid signal location;
a grid of the seventh transistor is connected to the N leveled pull-down gate all on signal location, a source electrode of the seventh transistor receives the first voltage signal, a drain electrode of the seventh transistor is connected to the N leveled scanning line;
the N leveled pull-down maintenance module comprises an eighth transistor, a ninth transistor and a tenth transistor;
a grid of the eighth transistor receives a positive scanning signal, a source electrode of the eighth transistor receives the second clock signal, a drain of the eighth transistor is connected to a grid of the tenth transistor;
a grid of the ninth transistor receives a negative scanning signal, a source electrode of the ninth transistor receives the third clock signal, a drain electrode of the ninth transistor is connected to a grid of the tenth transistor;
a source electrode of the tenth transistor receives a second voltage signal, a drain electrode of the tenth transistor is connected to the N leveled pull-down gate all on signal location.

6. The GOA circuit according to claim 5 , wherein the N leveled GOA unit also comprises a pull-down maintenance module, the pull-down maintenance module comprises an eleventh transistor, a grid of the eleventh transistor receives the second gate all on signal, a source electrode of the eleventh transistor receives the first voltage signal, a drain electrode of the eleventh transistor is connected to the N leveled pull-down gate all on signal location.

7. A display device, wherein the display device comprises a GOA circuit, the GOA circuit comprises a plurality of levels of GOA units, a N leveled GOA unit is applied to charge a N leveled scanning line of a display region of the display device, the N leveled scanning line is connected to a first gate all on signal and a second gate all on signal, which is applied to charge scanning lines corresponding to all the GOA units under control of the first gate all on signal and the second gate all on signal, where N is a positive integer that is larger than or equal to 1;
wherein the N leveled GOA unit comprises a N leveled pull-up control module, a N leveled pull-up module, a N leveled pull-down module and a N leveled pull-down maintenance module;
an output terminal of the N leveled pull-up control module is connected to a N leveled grid signal location;
an input terminal of the N leveled pull-up module is connected to the N leveled grid signal location, a control terminal of the N leveled pull-up module receives a first clock signal, an output terminal of the N leveled pull-up module is connected to the N leveled scanning line;
an input terminal of the N leveled pull-down module and a N leveled pull-down gate all on signal location are connected, a control terminal of the N leveled pull-down module receives a first voltage signal, an output terminal of a N leveled pull-down module is connected to the N leveled gri

Assignees

• Shenzhen China Star Optoelect
• Wuhan China Star Optoelectronics Technology Co Ltd
• Shenzhen China Star Optoelect
• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Xiao Juncheng
• Dai Ronglei
• Yan Yao
• Cao Shangcao

Classifications

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G3/3648

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G09G3/3674 Primary

  Details of drivers for scan electrodes · CPC title

• G09G2310/0202

  Addressing of scan or signal lines · CPC title

• G09G2310/0218

  with collection of electrodes in groups for n-dimensional addressing · CPC title