Multiplication operations in memory

Patent metadata

Field	Value
Publication number	US-9898252-B2
Application number	US-201514833680-A
Country	US
Kind code	B2
Filing date	Aug 24, 2015
Priority date	Sep 3, 2014
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

Examples of the present disclosure provide apparatuses and methods for performing multiplication operations in a memory. An example method comprises performing a multiplication operation on a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include a number operations performed without transferring data via an input/output (I/O) line.

First claim

What is claimed is:

1. A method for performing multiplication operations comprising:
performing a multiplication operation on:
a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array; and
a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array;

wherein the multiplication operation includes a number of logical operations performed by a controller operating sensing circuitry and without activating column decode lines coupled to the sensing circuitry.

2. The method of claim 1 , wherein performing the number of operations comprises performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations.

3. The method of claim 1 , further comprising generating a result from the performance of the multiplication operation and storing the result of the multiplication operation in the group of memory cells coupled to a third access line, wherein the group of memory cells comprises at least one of the group of memory cells coupled to the first access line and the group of memory cells coupled to the second access line.

4. The method of claim 1 , wherein the sensing circuitry is coupled to each of a number of columns of the number of sense lines.

5. The method of claim 4 , wherein the sensing circuitry comprises a sense amplifier and a compute component.

6. The method of claim 5 , wherein the sense amplifier comprises a primary latch and the compute component comprises a secondary latch.

7. The method of claim 1 , further comprising storing the first element as a bit-vector in the first group of memory cells coupled to the first access line wherein each memory cell in the first group of memory cells stores a respective bit of the bit-vector.

8. The method of claim 7 , further comprising storing the second element as a bit-vector in the second group of memory cells coupled to the first access line, wherein each memory cell in the second group of memory cells stores a respective bit of the bit-vector.

9. The method of claim 8 , wherein the first element is a first value and the second element is a second value.

10. An apparatus comprising:
a first group of memory cells coupled to a first access line of an array of memory cells and configured to store a first element;
a second group of memory cells coupled to a second access line of the array and configured to store a second element; and
a controller coupled to the array and configured to multiply the first element by the second element by controlling sensing circuitry to perform a number of operations without activating column decode lines coupled to the sensing circuitry.

11. The apparatus of claim 10 , wherein performing the number of operations comprises performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations.

12. The apparatus of claim 10 , wherein the controller is further configured to cause the sensing circuitry to determine a least-significant bit of the first element and the second element.

13. The apparatus of claim 10 , wherein the controller is further configured to cause the sensing circuitry to determine a most-significant bit of the first element and the second element.

14. The apparatus of claim 10 , comprising a third group of memory cells coupled to a third access line configured to store a result of the multiplication operation.

15. The apparatus of claim 10 , wherein the first group of memory cells and the second group of memory cells are coupled to a number of sense lines.

16. The apparatus of claim 15 , wherein:
a first memory cell of the first group of memory cells is coupled to a first sense line of the number of sense lines and stores a first bit of the first element; and
a first memory cell of the second group of memory cells is coupled to the first sense line and stores a first bit of the second element.

17. The apparatus of claim 16 , wherein:
a second memory cell of the first group of memory cells is coupled to a second sense line and stores a second bit of the first element; and
a second memory cell of the second group of memory cells is coupled to the second sense line and stores a second bit of the second element.

18. The apparatus of claim 17 , wherein a first memory cell of the third group of memory cells is coupled to the first sense line and stores a first bit of the result of the multiplication operation.

19. A method for performing multiplication operations comprising:
performing a multiplication operation, using a controller to operate sensing circuitry, on:
a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array; and
a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array;

wherein the multiplication operation includes a number of operations performed without activating column decode lines coupled to the sensing circuitry;
generating a result from performance of the multiplication operation; and
storing the result of the multiplication operation as a third element stored in a group of memory cells coupled to a third access line.

20. The method of claim 19 , wherein performing the multiplication operation comprises performing a number of iterations of operations using a dynamic mask element and a static mask element, wherein each iteration of operations comprises determining a data value contribution corresponding to a particular bit position of the first element and the second element to a multiplication result.

21. The method of claim 20 , wherein a first iteration of the number of iterations of operations comprises determining a data value contribution corresponding to a first bit position of the first element and the second element to a multiplication result without performing a shift operation for the dynamic mask element and the first element.

22. The method of claim 20 , wherein a second iteration of the number of iterations of operations comprises determining a data value contribution corresponding to a second bit position of the first element and the second element to the multiplication result by performing one shift operation for the dynamic mask element and the first element.

23. The method of claim 20 , wherein the dynamic mask indicates a least significant bit (LSB) position.

24. The method of claim 23 , comprising storing a particular data value in the LSB position of the dynamic mask.

25. The method of claim 24 , further comprising determining the LSB position by:
loading the particular data value into the sensing circuitry coupled to the number of sense lines;
shifting the particular data values stored in the sensing circuitry to the sensing circuitry one position to the right;
inverting the shifted particular data values and a data value other than the particular data value stored in a most significant bit position, wherein a result of the inversion is the particular data value being stored in the MSB position of the dynamic mask element; and
shifting the particular data value stored in the MSB position of the dynamic mask element to a right-most bit position of the dynamic mask element stored in a group of memory cells coupled to a dynamic mask access line.

26. The method of claim 23 , wherein the static mask element is determined

Assignees

• Micron Technology Inc

Inventors

• Tiwari Sanjay

Classifications

• G11C7/1006 Primary

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G06F2207/4802

  Special implementations · CPC title

• G06F7/523 Primary

  Multiplying only · CPC title