Generating and executing a control flow

Patent metadata

Field	Value
Publication number	US-2016196142-A1
Application number	US-201514980024-A
Country	US
Kind code	A1
Filing date	Dec 28, 2015
Priority date	Jan 7, 2015
Publication date	Jul 7, 2016
Grant date	—

Abstract

Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.

First claim

What is claimed is:

1 . An apparatus comprising:
a first device configured to generate control flow instructions; and a second device including:
an array of memory cells;
an execution unit to execute the control flow instructions; and
a controller configured to control an execution of the control flow instructions on data stored in the array.

2 . The apparatus of claim 1 , wherein the execution unit comprises sensing circuitry, the sensing circuitry comprising a number of sense amplifiers and a number of compute components comprising transistors formed on pitch with memory cells of the array.

3 . The apparatus of claim 2 , wherein the controller controls the execution of the control flow instructions by controlling the sensing circuitry to perform at least one logical operation without performing a sense line address access.

4 . The apparatus of claim 2 , wherein the at least one logical operation includes at least one logical operation selected from the group comprising:
an AND operation; an OR operation; and an INVERT operation.

5 . The apparatus of claim 4 , wherein the controller is located on the first device and is configured to translate the control flow instructions into the at least one logical operation.

6 . The apparatus of claim 4 , wherein the first device comprises a host having an arithmetic logic unit (ALU), and wherein none of the control flow instructions are executed by the ALU of the host.

7 . The apparatus of claim 4 , wherein the first device is one of a central processing unit (CPU), a system on a chip (SoC), an application specific integrated circuitry (ASIC), and a memory buffer.

8 . A method comprising:
dynamically generating control flow instructions on a first device; and executing the control flow instructions on a second device, the second device comprising:
an array of memory cells; and
a controller configured to control an execution of the control flow instructions on data stored in the array.

9 . The method of claim 8 , wherein generating the control flow instructions includes the first device fetching the control flow instructions from memory.

10 . The method of claim 9 , wherein the method includes decoding the control flow instructions on the first device.

11 . The method of claim 9 , wherein the method includes decoding at least partially decoding the control flow instructions on the first device and at least partially decoding the control flow instructions on the second device.

12 . The method of claim 11 , wherein the method includes the first device maintaining at least partial control over the control flow instructions while the control flow instructions are executed on the second device.

13 . The method of claim 8 , wherein executing the control flow instructions includes executing boolean control operations.

14 . The method of claim 8 , wherein executing the control flow instructions includes performing operations on data stored in the array other than a data write operation, a data read operation, and a data refresh operation.

15 . The method of claim 8 , wherein the method includes generating at least a portion of the control flow instructions on the first device while a different portion of the control flow instructions are being executed on the second device.

16 . The method of claim 8 , wherein dynamically generating control flow instructions includes:
generating a first number of control flow instructions that are associated with a first operation from a plurality of operations; and generating a second number of control flow instructions that are associated with a second operation from the plurality of operations.

17 . An apparatus comprising:
a processing device configured to generate a plurality of command flows; and a plurality of memory devices, each of the plurality of memory devices including:
a memory array;
sensing circuitry; and
a controller configured to operate the sensing circuitry to execute command flow instructions corresponding to the command flows on data stored in the memory array.

18 . The apparatus of claim 17 , wherein each of the respective plurality of memory devices is configured to execute command flow instructions corresponding to a different one of the plurality of command flows.

19 . The apparatus of claim 17 , wherein each of the plurality of command flows is generated serially.

20 . The apparatus of claim 17 , wherein the plurality of memory devices are configured to concurrently execute command flow instructions corresponding to different portions of at least one of the plurality of command flows.

21 . The apparatus of claim 17 , wherein the controller of each of the respective plurality of memory devices is configured to receive command flow instructions from the processing device.

22 . The apparatus of claim 17 , wherein:
the sensing circuitry of each of the respective plurality of memory devices comprises a plurality of sense amplifiers and a plurality of compute components; the plurality of compute components comprise transistors formed on pitch with memory cells of the respective memory array; and the sensing circuitry is operated by the respective controller to execute the command flow instructions, wherein executing the command flow instructions includes performing at least one logical operation without transferring data via an input/output line of the array.

23 . The apparatus of claim 22 , wherein the at least one logical operation is selected from the group including:
an AND operation; an operation; and an invert operation.

Assignees

• Micron Technology Inc

Inventors

• Wheeler Kyle B
• Murphy Richard C
• Manning Troy A
• Klein Dean A

Classifications

• G06F9/30058 Primary

  Conditional branch instructions · CPC title

• G06F9/30029

  Logical and Boolean instructions, e.g. XOR, NOT · CPC title

• G06F9/30

  Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F9/22) · CPC title

• G06F9/3005

  to perform operations for flow control · CPC title

• G06F9/3004

  to perform operations on memory · CPC title