Amplifier sharing technique for power reduction in analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-9893741-B2
Application number	US-201715463780-A
Country	US
Kind code	B2
Filing date	Mar 20, 2017
Priority date	Aug 7, 2015
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A dual delta-sigma modulator includes a first modulator, a second modulator, and a shared amplifier coupled to the first and second modulators. The first modulator includes an integrator configured to generate a first modulator output signal. The second modulator includes a second integrator configured to generate a second modulator output signal. The shared amplifier is configured to assist the first integrator integrating a difference between a first analog input signal and a first modulator output signal from the first modulator during a first period of time and to assist the second integrator integrate a difference between a second analog input signal and a second modulator output signal from the second modulator during a second period of time.

First claim

The invention claimed is:

1. A dual delta-sigma analog-to-digital converter (ADC), comprising:
a first delta-sigma modulator including a first integrator;
a second delta-sigma modulator including a second integrator;
an amplifier;
a first switch coupled between an input of the first integrator and an input of the amplifier;
a second switch coupled between an input of the second integrator and the input of the amplifier;
a third switch coupled between an output of the first integrator and an output of the amplifier;
a fourth switch coupled between an output of the second integrator and the output of the amplifier;
an interleaver having inputs coupled to respective outputs of the first and second delta-sigma modulators; and
a decimation filter having an input coupled to an output of the interleaver.

2. The dual delta-sigma ADC of claim 1 , wherein the input of the first integrator is a first input, the input of the second integrator is a first input, the input of the amplifier is a first input, the output of the first integrator is a first output, the output of the second integrator is a first output, and the output of the amplifier is a first output, the dual delta-sigma ADC further comprising:
a fifth switch coupled between a second input of the first integrator and a second input of the amplifier;
a sixth switch coupled between a second input of the second integrator and the second input of the amplifier;
a seventh switch coupled between a second output of the first integrator and a second output of the amplifier; and
an eighth switch coupled between a second output of the second integrator and the second output of the amplifier.

3. The dual delta-sigma ADC of claim 1 ,
wherein the first integrator is configured to integrate a difference between an analog input signal and a current modulator output signal of the first delta-sigma modulator during a first period of time, hold a first integrator output value during a second period of time, and generate a first modulator output signal,
wherein the second integrator is configured to hold a second integrator output value during the first period of time, integrate a difference between the analog input signal and a current modulator output signal of the second delta-sigma modulator during the second period of time, and generate a second modulator output signal,
wherein the amplifier is configured to assist the first delta-sigma modulator during the first period of time and to assist the second delta-sigma modulator during the second period of time,
wherein the interleaver is configured to interleave the first modulator output signal and the second modulator output signal to generate an interleaved output signal, and
wherein a decimation filter configured to filter and decimate the interleaved output signal to generate a digital output signal.

4. The dual delta-sigma ADC of claim 3 , wherein the decimation filter is configured to filter and decimate the interleaved output signal utilizing an over-sampling ratio (OSR).

5. The dual delta-sigma ADC of claim 3 , wherein the first delta-sigma modulator includes a first low power amplifier configured to:
integrate the difference between the analog input signal and the current modulator output signal of the first delta-sigma modulator during the first period of time with assistance of the amplifier; and
hold the first integrator output value without assistance of the amplifier during the second period of time.

6. The dual delta-sigma ADC of claim 5 , wherein the second delta-sigma modulator includes a second low power amplifier configured to:
integrate the difference between the analog input signal and the current modulator output signal of the second delta-sigma modulator during the second period of time with assistance of the amplifier; and
hold the second integrator output value without assistance of the amplifier during the second period of time.

7. The dual delta-sigma ADC of claim 6 , wherein approximately 85% of total integrator power of the first and second integrators of the dual delta-sigma modulator is consumed by the amplifier and the first low power amplifier and approximately 15% of total integrator power of the first and second integrators of the dual delta-sigma modulator is consumed by the second low power amplifier during the first period of time.

8. The dual delta-sigma ADC of claim 3 , wherein the decimation filter is further configured to attenuate high frequency out of band noise in the interleaved output signal prior to decimating the interleaved output signal.

9. The dual delta-sigma ADC of claim 3 , wherein the first period of time corresponds with a first sampling clock signal being HIGH, the first sampling clock signal configured to provide a sampling clock to the first delta-sigma modulator.

10. The dual delta-sigma ADC of claim 9 , wherein the second period of time corresponds with a second sampling clock signal being HIGH and the first sampling clock signal being LOW, the second sampling clock signal configured to provide a sampling clock to the second delta-sigma modulator.

11. The dual delta-sigma ADC of claim 3 , wherein the dual delta-sigma modulator is a single channel ADC.

12. A dual delta-sigma analog-to-digital converter (ADC), comprising:
a first delta-sigma modulator including a first integrator;
a second delta-sigma modulator including a second integrator;
an amplifier;
a first switch coupled between an input of the first integrator and an input of the amplifier;
a second switch coupled between an input of the second integrator and the input of the amplifier;
a third switch coupled between an output of the first integrator and an output of the amplifier; and
a fourth switch coupled between an output of the second integrator and the output of the amplifier.

13. The dual delta-sigma ADC of claim 12 , wherein the input of the first integrator is a first input, the input of the second integrator is a first input, the input of the amplifier is a first input, the output of the first integrator is a first output, the output of the second integrator is a first output, and the output of the amplifier is a first output, the dual delta-sigma ADC further comprising:
a fifth switch coupled between a second input of the first integrator and a second input of the amplifier;
a sixth switch coupled between a second input of the second integrator and the second input of the amplifier;
a seventh switch coupled between a second output of the first integrator and a second output of the amplifier; and
an eighth switch coupled between a second output of the second integrator and the second output of the amplifier.

14. The dual delta-sigma modulator of claim 12 ,
wherein the first delta-sigma modulator is configured to generate a first modulator output signal,
wherein the second delta-sigma modulator configured to generate a second modulator output signal, and
wherein the amplifier is configured to assist the first integrator integrating a difference between a first analog input signal and the first modulator output signal from the first delta-sigma modulator during a first period of time and to assist the second integrator integrating a difference between a second analog input signal and the second modulator output signal from the second delta-sigma modulator during a second period of time.

15. The dual delta-sigma modulator of claim 14 , wherein:
the first integrator is configured to receive the first analog input signal, integrate the difference between the first analog input signal and the first modulator output signal during the first period of time, and hold

Assignees

• Texas Instruments Inc

Inventors

• Cao Peng
• Gupta Amit Kumar
• Kidambi Srinivasan Venkata Krishnan

Classifications

• H03M3/496

  Details of sampling arrangements or methods · CPC title

• H03M3/344 Primary

  by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing · CPC title

• H03M3/468 Primary

  Interleaved, i.e. using multiple converters or converter parts for one channel, e.g. using Hadamard codes, pi-delta-sigma converters · CPC title

• H03M3/472

  Shared, i.e. using a single converter for multiple channels · CPC title