3D capacitor and method of manufacturing same

Patent metadata

Field	Value
Publication number	US-9893163-B2
Application number	US-201113289038-A
Country	US
Kind code	B2
Filing date	Nov 4, 2011
Priority date	Nov 4, 2011
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A 3D capacitor and method for fabricating a 3D capacitor is disclosed. An exemplary 3D capacitor includes a substrate including a fin structure, the fin structure including a plurality of fins. The 3D capacitor further includes an insulation material disposed on the substrate and between each of the plurality of fins. The 3D capacitor further includes a dielectric layer disposed on each of the plurality of fins. The 3D capacitor further includes a first electrode disposed on a first portion of the fin structure. The first electrode being in direct contact with a surface of the fin structure. The 3D capacitor further includes a second electrode disposed on a second portion of the fin structure. The second electrode being disposed directly on the dielectric layer and the first and second portions of the fin structure being different.

First claim

What is claimed is:

1. A device comprising:
a three-dimensional (3D) capacitor comprising:
a substrate including a top surface and a fin structure, the fin structure including first and second portions, the first portion of the fin structure including a first fin and the second portion of the fin structure including a second fin, each of the first and second fins including a fin-top surfaces and a sidewall surface;
a low-resistance layer on the top surface of the substrate, the fin-top surfaces of the first and second fins, and sidewall surfaces of the first and second fins;
an insulation material disposed over a first portion of the low-resistance layer over the top surface of the substrate between the first fin and the second fin;
a dielectric layer disposed over a second portion of the low-resistance layer, and over the insulation material;
a first electrode disposed over the first fin, the first electrode being in direct contact with the low-resistance layer on the fin-top surface of the first fin; and
a second electrode disposed over the dielectric layer that is disposed over the second fin,
wherein the first and second portions of the fin structure are different.

2. The device of claim 1 wherein the insulation material is disposed on opposing sides of the second fin.

3. The device of claim 1 wherein the first electrode is disposed in a central region of the first fin, and wherein the second electrode is disposed along the length of the second fin.

4. The device of claim 1 , wherein the low-resistance layer comprises boron, phosphorous, or arsenic.

5. A device comprising:
a three-dimensional (3D) capacitor comprising:
a substrate including a plurality of fins, the substrate including a top surface, the plurality of fins including fin-top surfaces and sidewall surfaces, wherein the top surface, the fin-top surfaces and sidewall surfaces comprises a low-resistance surface;
an insulation material disposed on the low-resistance surface over the top surface of the substrate between each of the plurality of fins;
a dielectric layer disposed on the low-resistance surface on each of the plurality of fins;
a first electrode disposed on a first portion of the plurality of fins, the first electrode being in direct contact with the low-resistance surface on only one fin, the one fin being of the first portion; and
a second electrode disposed on a second portion of the plurality of fins, the second electrode terminating in a central area between the first portion and the second portion and without contacting the dielectric layer disposed on sidewalls of the one fin,
wherein the first and second portions do not have any fins of the plurality of fins in common.

6. The device of claim 5 wherein the first and second electrodes include a material selected from the group consisting of Al, Cu, and W.

7. The device of claim 5 wherein the low resistance surface of the one fin of the first portion includes an implanted dopant selected from the group consisting of boron, phosphorus, and arsenic.

8. The device of claim 5 wherein the first electrode is in direct contact with the low resistance surface of the one fin of the first portion.

9. The device of claim 5 wherein the insulation material and the dielectric layer include different dielectric materials.

10. The device of claim 5 wherein the plurality of fins and the substrate include same materials.

11. The device of claim 5 the second portion includes a low resistance surface.

12. The device of claim 5 , wherein the low-resistance surface comprises boron, phosphorous, or arsenic.

13. A device comprising:
a three-dimensional (3D) capacitor comprising:
a substrate including a plurality of fins, the plurality of fins including a first portion including one or more fins and a second portion including two or more fins directly adjacent to each other;
an insulation material disposed over the substrate and between each fin of the plurality of fins;
a dielectric layer traversing each fin of the plurality of fins and the insulation material between each fin of the plurality of fins;
a first electrode extending through the dielectric layer traversing the one or more fins of the first portion of the plurality of fins, the first electrode being in physical contact with a conductive surface of only one fin, the one fin being of the one or more fins of the first portion of the plurality of fins; and
a second electrode traversing the dielectric layer disposed over the two or more fins of the second portion of the plurality of fins without contacting a portion of the dielectric layer traversing sidewalls of the one or more fins of the first portion of the plurality of fins, the second electrode traversing the dielectric layer and the insulation material disposed between the two or more fins of the second portion of the plurality of fins,
wherein a continuous low resistance surface traverses the one or more fins of the first portion of the plurality of fins and extends to and traverses the two or more fins of the second portion of the plurality of fins.

14. The device of claim 13 wherein the first electrode is disposed in a central region of the first portion.

15. The device of claim 13 wherein the first and the second electrodes include a material selected from the group consisting of Al, Cu, and W.

16. The device of claim 13 wherein each of the two or more fins of the second portion of the plurality of fins includes a low resistance surface.

17. The device of claim 13 wherein the substrate is a silicon-on-insulator (SOI) substrate.

18. The device of claim 13 , wherein the continuous low resistance surface comprises boron, phosphorous, or arsenic.

Assignees

• Liu Chi Wen
• Wang Chao Hsiung
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liu Chi Wen
• Wang Chao Hsiung

Classifications

• H10D1/047 Primary

  of conductor-insulator-semiconductor capacitors, e.g. trench capacitors · CPC title

• H10D1/043

  using patterning processes to form electrode extensions, e.g. etching · CPC title

• H10D1/665

  Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors · CPC title

• H10D1/716 Primary

  having vertical extensions · CPC title

• H01L29/94

  Electricity · mapped topic