Pre-plated substrate for die attachment

Patent metadata

Field	Value
Publication number	US-9893027-B2
Application number	US-201615093713-A
Country	US
Kind code	B2
Filing date	Apr 7, 2016
Priority date	Apr 7, 2016
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A method for attaching a semiconductor die to a substrate includes providing a substrate that includes an attachment layer at a surface of the substrate. The attachment layer is covered by a protective flash plating layer. The protective flash plating layer has a reflow temperature less than or equal to a reflow temperature of the attachment layer. The method further includes preheating the substrate to a temperature greater than or equal to a reflow temperature of the attachment layer, attaching a semiconductor die to the attachment layer, and cooling the substrate and semiconductor die.

First claim

The invention claimed is:

1. A method for attaching a semiconductor die to a substrate, the method comprising:
providing a substrate, the substrate including an attachment layer at a surface of the substrate, the attachment layer directly overlaid by a protective flash plating layer to cover the attachment layer, the protective flash plating layer having a reflow temperature less than or equal to a reflow temperature of the attachment layer;
preheating the substrate to a temperature greater than or equal to a reflow temperature of the attachment layer, wherein the protective flash plating layer melts during the preheating to permit access to the attachment layer;
attaching a semiconductor die to the attachment layer while the flash plating layer is melted, wherein the semiconductor die and the attachment layer are in direct contact; and cooling the substrate and semiconductor die.

2. The method of claim 1 , wherein the protective flash plating layer is made from gold.

3. The method of claim 2 , wherein the protective flash plating layer has a thickness in a region above a surface of the attachment layer of about 10 micro-inches or less.

4. The method of claim 1 , wherein the attachment layer is made from a combination of gold and tin.

5. The method of claim 1 , wherein the substrate is preheated to a temperature of about 310° C.

6. The method of claim 1 , wherein the semiconductor die is formed of gallium nitride.

7. The method of claim 1 , wherein the substrate is gold plated.

8. The method of claim 1 , wherein the substrate and semiconductor die are cooled to a temperature below about 260° C.

9. The method of claim 1 , further comprising scrubbing the semiconductor die on the attachment layer.

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Abdo David F
• Sathiapalan Sivanesan A/L

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W80/041

  Thermally treating · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/07341

  Controlling the bonding environment, e.g. atmosphere composition or temperature · CPC title