Semiconductor chip with anti-reverse engineering function

Patent metadata

Field	Value
Publication number	US-9893023-B2
Application number	US-201715606178-A
Country	US
Kind code	B2
Filing date	May 26, 2017
Priority date	Sep 23, 2015
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.

First claim

What is claimed is:

1. An anti-reverse engineering semiconductor method, comprising:
providing a semiconductor substrate;
forming a stack of wiring levels from a first wiring level to an intermediate wiring level, said first wiring level closest to said semiconductor substrate and said intermediate wiring level furthest from said semiconductor substrate;
forming active devices contained in said semiconductor substrate and said first wiring level, each wiring level of said stack of wiring levels comprising a dielectric layer containing electrically conductive wire;
forming one or more trenches extending from said intermediate wiring level, through said first wiring level into said semiconductor substrate;
forming a liner on sidewalls and a bottom of said one or more trenche such that said one or more trenches comprises an open space; and
(i) filling said open space of said one or more trenches with a first chemical agent that can cause damage to or destroy portions of at least one wiring level of said stack of wiring levels or (ii) filling a first group of said one or more trenches with a second chemical agent and a filling a second group of said one more trenches a third chemical agent, a mixture of said second chemical agent and said third chemical agent generating a fourth chemical agent that can cause damage to or destroys portions of at least one wiring level of said stack of wiring levels;
forming a cap sealing a top of said open space of said one or more trenches, wherein each of said liner and said cap is configured to be damaged during a reverse engineering process such that said one or more trenches is exposed to said at least one wiring level of said stack of wiring levels; and
forming one or more additional wiring levels on top of said intermediate wiring level.

2. The method of claim 1 , wherein said one or more trenches do not extend completely through said semiconductor substrate.

3. The method of claim 1 , wherein each of said one or more trenches is filled with said first chemical agent and said first chemical agent can attack wires, dielectric layers or both wires and dielectric materials of said at least one wiring level of said stack of wiring levels.

4. The method of claim 1 , wherein said chemical agent generates a fifth chemical agent that can chemically attack wires, dielectric layers or both wires and dielectric materials of said at least one wiring level of said stack of wiring levels when said chemical agent is exposed to air, oxygen or water.

5. The method of claim 1 , wherein said mixture of second chemical agent and said third chemical agent generates heat or wherein said mixture of second chemical agent and said third chemical agent generates a material that expands in volume.

Assignees

• IBM

Inventors

• Cooney Iii Edward C
• Chen Fen
• Pratt Jonathan M
• Ritter Jason P
• Spinney Patrick S
• Tilley Anna

Classifications

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W42/40 Primary

  protecting against tampering, e.g. unauthorised inspection or reverse engineering · CPC title

• H01L23/5226

  Electricity · mapped topic