Methods for forming stacked capacitors with fuse protection
US-9385079-B2 · Jul 5, 2016 · US
US9892957B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9892957-B2 |
| Application number | US-201514659170-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 16, 2015 |
| Priority date | Mar 16, 2015 |
| Publication date | Feb 13, 2018 |
| Grant date | Feb 13, 2018 |
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A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first dielectric layer over the substrate. The semiconductor device structure includes a second dielectric layer over the first dielectric layer. The first dielectric layer and the second dielectric layer are made of different materials. The semiconductor device structure includes a conductive via structure passing through the first dielectric layer and penetrating into the second dielectric layer. The conductive via structure has a first portion and a second portion. The first portion and the second portion are in the first dielectric layer and the second dielectric layer respectively. The first portion has a first end portion facing the substrate. A first width of the first end portion is greater than a second width of the second portion.
Opening claim text (preview).
What is claimed is: 1. A semiconductor device structure, comprising: a substrate; a first dielectric layer over the substrate; a second dielectric layer over the first dielectric layer, wherein the first dielectric layer and the second dielectric layer are made of different materials; and a conductive via structure passing through the first dielectric layer and penetrating into the second dielectric layer, wherein the conductive via structure has a first portion and a second portion, the first portion and the second portion are in the first dielectric layer and the second dielectric layer respectively, the first portion has a first end portion facing the substrate, a first width of the first end portion is greater than a second width of the second portion, the first portion further has a second end portion adjacent to the second portion, and the first width of the first end portion is greater than a third width of the second end portion. 2. The semiconductor device structure as claimed in claim 1 , further comprising: a conductive line in the second dielectric layer and over the conductive via structure. 3. The semiconductor device structure as claimed in claim 2 , wherein the second portion of the conductive via structure is in direct contact with the conductive line. 4. The semiconductor device structure as claimed in claim 2 , wherein the first width of the first end portion is less than a fourth width of the conductive line. 5. The semiconductor device structure as claimed in claim 1 , further comprising: a third dielectric layer between the substrate and the first dielectric layer; and a conductive line in the third dielectric layer and under the conductive via structure, wherein the conductive line is electrically connected to the conductive via structure. 6. The semiconductor device structure as claimed in claim 5 , wherein the first width of the first end portion is less than a fourth width of the conductive line. 7. The semiconductor device structure as claimed in claim 1 , wherein the conductive via structure further passes through the second dielectric layer. 8. A semiconductor device structure, comprising: a substrate; a first dielectric layer over the substrate; a second dielectric layer over the first dielectric layer, wherein the first dielectric layer and the second dielectric layer are made of different materials; a conductive via structure passing through the first dielectric layer and penetrating into the second dielectric layer, wherein the conductive via structure has a first portion and a second portion, the first portion and the second portion are in the first dielectric layer and the second dielectric layer respectively, a first width of the first portion continuously increases in a direction from the second dielectric layer to the substrate, the first portion has a first end portion, and the first end portion faces the substrate; and a conductive line in the second dielectric layer and over the conductive via structure, wherein a second width of the first end portion is greater than a third width of the second portion, and the second width of the first end portion is less than a fourth width of the conductive line. 9. The semiconductor device structure as claimed in claim 8 , wherein the first portion further has a second end portion, the second end portion is adjacent to the second portion, and the second width of the first end portion is greater than a fifth width of the second end portion. 10. The semiconductor device structure as claimed in claim 8 , further comprising: an adhesive layer between the first dielectric layer and the second dielectric layer, wherein the conductive via structure further passes through the adhesive layer. 11. The semiconductor device structure as claimed in claim 10 , wherein the adhesive layer, the first dielectric layer, and the second dielectric layer are made of different materials. 12. The semiconductor device structure as claimed in claim 8 , wherein the first dielectric layer comprises silicon carbide or silicon nitride. 13. The semiconductor device structure as claimed in claim 8 , further comprising: a third dielectric layer between the substrate and the first dielectric layer; and a conductive structure in the third dielectric layer and under the conductive via structure, wherein the conductive structure is electrically connected to the conductive via structure. 14. A method for forming a semiconductor device structure, comprising: forming a first dielectric layer over a substrate; forming a second dielectric layer over the first dielectric layer, wherein the first dielectric layer and the second dielectric layer are made of different materials; forming a through hole in the first dielectric layer and a hole in the second dielectric layer, wherein the through hole is connected to the hole, the through hole has a first end opening and a second end opening, the first end opening faces the substrate, the second end opening faces the hole, a first width of the first end opening is greater than a second width of the second end opening; forming a conductive via structure in the through hole and the hole; before the formation of the conductive via structure, forming a trench in the second dielectric layer, wherein the trench is connected to the hole; and during the formation of the conductive via structure, forming a conductive line in the trench. 15. The method for forming a semiconductor device structure as claimed in claim 14 , wherein the formation of the through hole and the hole comprises: forming a mask layer over the second dielectric layer, wherein the mask layer has an opening exposing a first portion of the second dielectric layer; and performing a dry etching process to remove the first portion of the second dielectric layer and a second portion of the first dielectric layer below the first portion. 16. The method for forming a semiconductor device structure as claimed in claim 15 , wherein the dry etching process comprises a plasma etching process. 17. The method for forming a semiconductor device structure as claimed in claim 14 , wherein the first width of the first end opening is less than a third width of the trench.
by chemical means · CPC title
by chemical means · CPC title
using masks for insulating materials · CPC title
of multilayered thin functional dielectric layers · CPC title
using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title
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