Memory devices having signal routing structures at bonding interfaces
US-2024404976-A1 · Dec 5, 2024 · US
US8946004B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8946004-B2 |
| Application number | US-54414409-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 19, 2009 |
| Priority date | Mar 13, 2009 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
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Official abstract text for this publication.
A contact portion of wiring and a method of manufacturing the same are disclosed. A contact portion of wiring according to an embodiment includes: a substrate; a conductive layer disposed on the substrate; an interlayer insulating layer disposed on the conductive layer and having a contact hole; a metal layer disposed on the conductive layer and filling the contact hole; and a transparent electrode disposed on the interlayer insulating layer and connected to the metal layer, wherein the interlayer insulating layer includes a lower insulating layer and an upper insulating layer disposed on the lower insulating layer, the lower insulating layer is undercut at the contact hole, and the metal layer fills in the portion where the lower insulating layer is undercut.
Opening claim text (preview).
What is claimed is: 1. A method for manufacturing a contact portion of wiring, the method comprising: forming a conductive layer on a substrate; sequentially forming a lower insulating layer and an upper insulating layer on the conductive layer; patterning the upper insulating layer to form a primary contact hole exposing the lower insulating layer; etching the lower insulating layer by using the patterned upper insulating layer as a mask to form a contact hole exposing the…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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