Multi-time programmable non-volatile memory cell and associated circuits

Patent metadata

Field	Value
Publication number	US-9892787-B2
Application number	US-201715466771-A
Country	US
Kind code	B2
Filing date	Mar 22, 2017
Priority date	Apr 5, 2016
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A multi-time programmable memory cell has a differential multi-time programmable memory cell and a second-level latch cell. The differential multi-time programmable memory cell provides a first balance signal and a second balance signal, and the second-level latch cell receives the first balance signal and the second balance signal and provides an output signal according to the first balance signal and the second balance signal based on a first latch control signal and a second latch control signal.

First claim

We claim:

1. A multi-time programmable memory cell, comprising:
a differential multi-time programmable memory cell, comprising a memory module configured to store a data, the differential multi-time programmable memory cell is configured to erase the data stored in the memory module via an erase operation, write the data into the memory module via a write operation, read out the data stored in the memory module and provide a first balance signal and a second balance signal accordingly via a read operation, and load a first load control signal and a second load control signal and provide the first balance signal and the second balance signal via a load operation; and
a second-level latch cell, coupled to the differential multi-time programmable memory cell to receive the first balance signal and the second balance signal, and the second-level latch cell is configured to provide an output signal based on the first balance signal, the second balance signal, a first latch control signal and a second latch control signal; wherein
the second-level latch cell is configured to generate a sampled signal via sampling the first balance signal and the second balance signal, and the second-level latch cell is configured to provide the output signal based on the sampled signal; and wherein
the sampled signal is being stored during when the first latch control signal is at a first state and the second latch control signal is at a second state, and the sampled signal is being held during when the first latch control signal is in the second state and the second latch control signal is in the first state.

2. The multi-time programmable memory cell of claim 1 , wherein the second-level latch cell further comprises:
a sample control module, configured to receive the first latch control signal and the second latch control signal, and provide a first sample control signal and a second sample control signal in response to the first latch control signal and the second latch control signal; and
a balance module, coupled to the differential multi-time programmable memory cell to receive the first balance signal and the second balance signal, and coupled to the sample control module to receive the first sample control signal and the second sample control signal, and the balance module is configured to provide the sampled signal via sampling the first balance signal and the second balance signal under control of the first sample control signal and the second sample control signal.

3. The multi-time programmable memory cell of claim 2 , wherein the balance module further comprises:
a first complementary metal-oxide-semiconductor (CMOS) inverter, comprising a first P-type metal oxide semiconductor field effect transistor (PMOS) and a first N-type metal oxide semiconductor field effect transistor (NMOS), both the first PMOS and the first NMOS have a drain, a source and a gate respectively, and the gate of the first PMOS and the gate of the first NMOS are coupled together to receive the first balance signal; and
a second CMOS inverter, comprising a second PMOS and a second NMOS, both the second PMOS and the second NMOS have a drain, a source and a gate respectively, and the gate of the second PMOS and the gate of the second NMOS are coupled together to receive the second balance signal; wherein
the source of the first PMOS and the source of the second PMOS are coupled together to receive the first sample control signal, and the source of the first NMOS and the source of the second NMOS are coupled together to receive the second sample control signal, the drain of the first PMOS is coupled to the drain of the first NMOS, the drain of the second PMOS is coupled to the drain of the second NMOS, and one of the drain of the first PMOS and the drain of the second PMOS is configured to provide the sampled signal.

4. The multi-time programmable memory cell of claim 2 , wherein the sample control module further comprises:
a third PMOS, having a drain, a source and a gate, wherein the source of the third PMOS is coupled to a supply voltage, the gate of the third PMOS is configured to receive the second latch control signal, and the drain of the third PMOS is configured to provide the first sample control signal; and
a third NMOS, having a drain, a source and a gate, wherein the source of the third NMOS is coupled to a logic ground, the gate of the third NMOS is configured to receive the first latch control signal, and the drain of the third NMOS is configured to provide the second sample control signal.

5. The multi-time programmable memory cell of claim 2 , wherein the second-level latch cell further comprises:
a hold control module, configured to receive the first latch control signal and the second latch control signal, and configured to provide a first hold control signal and a second hold control signal in response to the first latch control signal and the second latch control signal; and
a single-ended output module, configured to receive the sampled signal, the first hold control signal, and the second hold control signal, and provide the output signal in response to the sampled signal under control of the first latch control signal and the second latch control signal.

6. The multi-time programmable memory cell of claim 1 , wherein the second-level latch cell further comprises:
a balance module, having a first input terminal configured to receive the first balance signal, a second input terminal configured to receive the second balance signal, a third input terminal, a fourth input terminal, and an output terminal configured to provide a sampled signal via sampling the first balance signal and the second balance signal when the first latch control signal is in the first state and the second latch control signal is in the second state; and
a single-ended output module, having a first input terminal coupled to the balance module to receive the sampled signal, a second input terminal, a third input terminal, a fourth input terminal, a fifth input terminal, and an output terminal configured to provide the output signal in response to the sampled signal when the first latch control signal is in the second state and the second latch control signal is in the first state.

7. The multi-time programmable memory cell of claim 6 , wherein the balance module further comprises:
a first CMOS inverter, comprising a first PMOS and a first NMOS, both the first PMOS and the first NMOS have a drain, a source and a gate respectively, and the gate of the first PMOS and the gate of the first NMOS are coupled together to receive the first balance signal; and
a second CMOS inverter, comprising a second PMOS and a second NMOS, both the second PMOS and the second NMOS have a drain, a source and a gate respectively, and the gate of the second PMOS and the gate of the second NMOS are coupled together to receive the second balance signal; wherein
the source of the first PMOS and the source of the second PMOS are coupled together as the third input terminal of the balance module, the source of the first NMOS and the source of the second NMOS are coupled together as the fourth input terminal of the balance module, the drain of the first PMOS is coupled to the drain of the first NMOS, the drain of the second PMOS is coupled to the drain of the second NMOS, and one of the drain of the first PMOS and the drain of the second PMOS is configured as the output terminal of the balance module.

8. The multi-time programmable memory cell of claim 6 , wherein the second-level latch cell further comprises:
a third PMOS, having a drain, a source and a gate, wherein the source of the third PMOS is coupled to a supply voltage, the gate of the third PMOS is configured to receive the second latch control signal, and the drain of t

Assignees

• Chengdu Monolithic Power Sys

Inventors

• Chen Da
• Braun Eric

Classifications

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/0433 Primary

  comprising cells containing a single floating gate transistor and one or more separate select transistors · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C7/067

  Single-ended amplifiers · CPC title

• G11C11/412

  using field-effect transistors only · CPC title