One-time programmable memory cell and circuit

Patent metadata

Field	Value
Publication number	US-9245647-B2
Application number	US-201414320256-A
Country	US
Kind code	B2
Filing date	Jun 30, 2014
Priority date	Jun 30, 2014
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

An OTP memory cell and an OTP memory circuit. The OTP memory cell having a memory module, a write module, a read module, and a load module. Data may be written into the memory module once the write module is active; and data may be read out of the memory module once the read module is active. The OTP memory cell may also have a first latch module and a second latch module.

First claim

We claim:

1. A One-Time Programmable (OTP) memory cell, comprising:
a memory module having a first terminal and a second terminal, wherein the memory module is configured to store data;
a write module having a first input terminal, a second input terminal, a first output terminal and a second output terminal, wherein the write module is configured to write data into the memory module, and wherein the first input terminal of the write module is configured to receive a first write signal, and wherein the second input terminal of the write module is configured to receive a second write signal, and wherein the first output terminal of the write module is configured to provide a first write-in signal to the first terminal of the memory module, and wherein the second output terminal of the write module is configured to provide a second write-in signal to the second terminal of the memory module, and wherein the first write signal and the second write signal are logic complementary, and wherein the first write-in signal and the second write-in signal represent the data needed to store in the memory module, and wherein the first write-in signal and the second write-in signal are logic complementary;
a read module having a first input terminal, a second input terminal, a third input terminal, a first output terminal and a second output terminal, wherein the read module is configured to read out data from the memory module, and wherein the first input terminal of the read module is coupled to the first terminal of the memory module, and wherein the second input terminal of the read module is coupled to the second terminal of the memory module, and wherein the third input terminal is configured to receive a read signal, and wherein the first output terminal of the read module is configured to provide a first read-out signal, and wherein the second output terminal of the read module is configured to provide a second read-out signal wherein the read signal is an analog signal, and wherein the first read-out signal and the second read-out signal represent data stored in the memory module, and wherein the first read-out signal and the second read-out signal are logic complementary;
a load module having a first input terminal, a second input terminal, a first output terminal and a second output terminal, wherein the first input terminal of the load module is configured to receive a first load signal, and wherein the second input terminal of the load module is configured to receive a second load signal, and wherein the first output terminal of the load module is configured to provide a first load out signal, and wherein the second output terminal of the load module is configured to provide a second load out signal, and wherein the first load signal and the second load signal are logic complementary, and wherein the first load out signal and the second load out signal are logic complementary;
a first latch module having a first input terminal, a second input terminal, a first output terminal and a second output terminal, wherein the first input terminal of the first latch module is configured to receive the first read-out signal of the read module and/or the first load out signal of the load module, and wherein the second input terminal of the first latch module is configured to receive the second read-out signal of the read module and/or the second load out signal of the load module, and wherein the first output terminal of the first latch module is coupled to a first output terminal of the OTP memory cell to provide a first output signal of the OTP memory cell, and wherein the second output terminal of the first latch module is coupled to a second output terminal of the OTP memory cell to provide a second output signal of the OTP memory cell, and wherein the first output signal of the OTP memory cell and the second output terminal of the OTP memory cell are logic complementary; and
a first multiplexer having a first input terminal, a second input terminal, a third input terminal, a first output terminal and a second output terminal, wherein the first input terminal of the first multiplexer is configured to receive the first output signal of the OTP memory circuit, and wherein the second input terminal of the first multiplexer is configured to receive the second output signal of the OTP memory circuit, and wherein the third input terminal of the first multiplexer is configured to receive a control signal, and wherein the control signal is an analog signal, and wherein the first output terminal of the first multiplexer is configured to provide a first output signal as the first write signal, and wherein the second output terminal of the first multiplexer is configured to provide a second output signal as the second write signal.

2. The OTP memory cell of claim 1 , wherein the memory module has a differential structure comprising a first Floating Gate Metal-Oxide Semiconductor transistor (FAMOS) and a second FAMOS, wherein the first FAMOS and the second FAMOS have a source, a drain and a floating gate respectively, and wherein the source of the first FAMOS and the source of the second FAMOS are connected together to receive a supply voltage; and wherein the drain of the first FAMOS is configured to operate as the first terminal of the memory module; and wherein the drain of the second FAMOS is configured to operate as the second terminal of the memory module.

3. The OTP memory cell of claim 1 , wherein the write module has a differential structure comprising a first N-type Metal-Oxide Semiconductor transistor (NMOS) and a second NMOS, wherein the first NMOS and the second NMOS have a source, a drain and a gate respectively, and wherein the source of the first NMOS and the source of the second NMOS are connected to a logic ground; and wherein the drain of the first NMOS is configured to operate as the first output terminal of the write module, and is coupled to the first terminal of the memory module; and wherein the drain of the second NMOS is configured to operate as the second output terminal of the write module, and is coupled to the second terminal of the memory module; and wherein the gate of the first NMOS is configured to operate as the first input terminal of the write module, and is configured to receive the first write signal; and wherein the gate of the second NMOS is configured to operate as the second input terminal of the write module, and is configured to receive the second write signal.

4. The OTP memory cell of claim 1 , wherein the read module has a differential structure comprising a first P-type Metal-Oxide Semiconductor transistor (PMOS) and a second PMOS, wherein the first PMOS and the second PMOS have a source, a drain and a gate respectively, and wherein the source of the first PMOS is configured to operate as the first input terminal of the read module, and is coupled to the first terminal of the memory module; and wherein the source of the second PMOS is configured to operate as the second input terminal of the read module, and is coupled to the second terminal of the memory module; and wherein the gate of the first PMOS and the gate of the second PMOS is connected together as the third input terminal of the read module to receive the read signal; and wherein the drain of the first PMOS is configured to operate as the first output terminal of the read module, and is configured to provide the first read-out signal; and wherein the drain of the second PMOS is configured to operate as the second output terminal of the read module, and is configured to provide the second read-out signal.

5. The OTP memory cell of claim 1 , wherein the load module has a differential structure comprising a third PMOS and a fourth PMOS, wherein the third PMOS and the fourth PMOS have a source, a drain and a gate respectively, and wherein the drain of the t

Assignees

• Chengdu Monolithic Power Sys

Inventors

• Braun Eric
• Chen Da

Classifications

• H01L27/112

  Electricity · mapped topic

• G11C17/16

  using electrically-fusible links · CPC title

• H01L2924/0002

  Electricity · mapped topic

• H01L2924/00

  Electricity · mapped topic

• H01L27/105

  Electricity · mapped topic