Semiconductor device, test method thereof, and system

Patent metadata

Field	Value
Publication number	US-9330786-B2
Application number	US-201113012360-A
Country	US
Kind code	B2
Filing date	Jan 24, 2011
Priority date	Jan 28, 2010
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

A semiconductor device includes a plurality of chips comprising a plurality of I/O terminals connected in common via through electrodes. Each of the chips includes an I/O compression circuit operable to output a compression result obtained by compression of data of a plurality of internal data buses to a first I/O terminal of the plurality of I/O terminals. Each of the chips also includes a test control circuit having a register group that sets the number of the first I/O terminal. Setting information that assigns different first I/O terminals to different chips is set in the register group. Each of the chips inputs or outputs data with use of the number of the I/O terminal that is different from those in other chips. Thus, the I/O compression circuits can concurrently perform an I/O compression test in parallel in the plurality of chips without a bus fight.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first chip and a second chip,
wherein a plurality of I/O terminals of the first chip and a plurality of I/O terminals of the second chip are connected in common,
each of the first and second chips includes:
an I/O compression circuit operable to output a compression result obtained by compression of data of a plurality of internal data buses to a first I/O terminal of the plurality of I/O terminals in a test mode, and
a test control circuit operable to control the I/O compression circuit, the test control circuit comprising a number setting register operable to set the number of the first I/O terminal of the plurality of I/O terminals so that the number of the first I/O terminal of the first chip is different from the number of the first I/O terminal of the second chip, and

each of the first and second chips is operable to concurrently input data from or output data to an exterior or an interior of the semiconductor device in parallel so that different first I/O terminals are used in different chips with the I/O compression circuit activated in the test mode by the test control circuit.

2. The semiconductor device as recited in claim 1 , wherein the first chip and the second chip are stacked on each other, the plurality of I/O terminals of the first chip and the plurality of I/O terminals of the second chip are connected in common via through electrodes of the first chip and the second chip.

3. The semiconductor device as recited in claim 1 , wherein the I/O compression circuit includes:
a logical circuit operable to receive a plurality of data of the plurality of internal data buses and to output the compression result in a reading mode of the test mode, and
a first switch circuit that establishes electric conduction in the test mode, the first switch circuit being connected between the plurality of I/O terminals and an output node of the logical circuit.

4. The semiconductor device as recited in claim 3 , wherein the I/O compression circuit includes a second switch circuit operable to electrically connect the output node of the logical circuit to a plurality of input nodes of the logical circuit in a writing mode of the test mode.

5. The semiconductor device as recited in claim 1 , wherein the I/O compression circuit comprises a plurality of first I/O compression circuits corresponding to a plurality of groups into which the plurality of I/O terminals is divided, and
each of the plurality of first I/O compression circuits includes:
a first logical circuit operable to receive a plurality of data of the plurality of internal data buses corresponding to the plurality of groups and to output the corresponding compression result to the plurality of groups in a reading mode of the test mode, and
a first switch circuit connected between the plurality of I/O terminals corresponding to the plurality of groups and an output node of the first logical circuit, the first switch circuit being operable to electrically connect the output node to one of the plurality of I/O terminals corresponding to the plurality of groups in the test mode.

6. The semiconductor device as recited in claim 5 , wherein the first I/O compression circuit further includes a second switch circuit operable to electrically connect the output node of the first logical circuit to a plurality of input nodes of the first logical circuit in a writing mode of the test mode.

7. The semiconductor device as recited in claim 5 , wherein the test control circuit further includes a compression ratio setting register operable to provide different compression ratios of the data,
the I/O compression circuit includes:
a second I/O compression circuit that realizes a first compression ratio of the plurality of I/O terminals, and
the plurality of first I/O compression circuits that realize a second compression ratio lower than the first compression ratio, the plurality of first I/O compression circuits corresponding to the plurality of groups, the compression ratio setting register selecting one of the first compression ratio and the second compression ratio, and

the second I/O compression circuit includes:
a second logical circuit operable to receive a plurality of data of the plurality of internal data buses and to output the compression result in the reading mode of the test mode, and
a third switch circuit connected between the plurality of I/O terminals and an output node of the second logical circuit, the third switch circuit being operable to electrically connect the output node of the second logical circuit to one of the plurality of I/O terminals in the test mode.

8. The semiconductor device as recited in claim 7 , wherein the second I/O compression circuit further includes a fourth switch circuit operable to electrically connect the plurality of I/O terminals to the plurality of internal data buses, respectively, in a writing mode of the test mode.

9. A system comprising a semiconductor device and a controller connected to the semiconductor device via a command bus and an I/O bus, the semiconductor device comprising a first chip and a second chip,
wherein a plurality of I/O terminals of the first chip and a plurality of I/O terminals of the second chip are connected in common,
each of the first and second chips includes:
an I/O compression circuit operable to output a compression result obtained by compression of data of a plurality of internal data buses to a first I/O terminal of the plurality of I/O terminals in a test mode, and
a test control circuit operable to control the I/O compression circuit, the test control circuit comprising a number setting register operable to set the number of the first I/O terminal of the plurality of I/O terminals so that the number of the first I/O terminal of the first chip is different from the number of the first I/O terminal of the second chip, and

each of the first and second chips is operable to concurrently input data from or output data to an exterior or an interior of the semiconductor device in parallel so that different first I/O terminals are used in different chips with the I/O compression circuit activated in the test mode by the test control circuit.

10. The system as recited in claim 9 , wherein the first chip and the second chip are stacked on each other, the plurality of I/O terminals of the first chip and the plurality of I/O terminals of the second chip are connected in common via through electrodes of the first chip and the second chip.

11. The system as recited in claim 9 , wherein the I/O compression circuit includes:
a logical circuit operable to receive a plurality of data of the plurality of internal data buses and to output the compression result in a reading mode of the test mode, and
a first switch circuit that establishes electric conduction in the test mode, the first switch circuit being connected between the plurality of I/O terminals and an output node of the logical circuit.

12. The system as recited in claim 11 , wherein the I/O compression circuit includes a second switch circuit operable to electrically connect the output node of the logical circuit to a plurality of input nodes of the logical circuit in a writing mode of the test mode.

13. The system as recited in claim 9 , wherein the I/O compression circuit comprises a plurality of first I/O compression circuits corresponding to a plurality of groups into which the plurality of I/O terminals is divided, and
each of the plurality of first I/O compression circuits includes:
a first logical circuit operable to receive a plurality of data of the plurality of internal data buses corresponding to

Assignees

• Uetake Satoshi
• Uo Yuji
• Ps4 Luxco Sarl

Inventors

• Uetake Satoshi
• Uo Yuji

Classifications

• H10W72/07251

  characterised by changes in properties of the bump connectors during connecting · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C29/40 Primary

  using compression techniques · CPC title

• H01L2924/00

  Electricity · mapped topic