Test structures and testing methods for semiconductor devices

Patent metadata

Field	Value
Publication number	US-9891273-B2
Application number	US-201113172432-A
Country	US
Kind code	B2
Filing date	Jun 29, 2011
Priority date	Jun 29, 2011
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

Test structures, methods of manufacturing thereof, and testing methods for semiconductors are disclosed. In one embodiment, a test structure for semiconductor devices includes a printed circuit board (PCB), a probe region, and a compliance mechanism disposed between the PCB and the probe region. A plurality of wires is coupled between the PCB and the probe region. End portions of the plurality of wires proximate the probe region are an integral part of the probe region.

First claim

What is claimed is:

1. A test structure for semiconductor devices, the test structure comprising:
a compliance mechanism disposed between a printed circuit board (PCB) and a probe region;
a fix ring coupled to the PCB;
an aperture extending completely through the PCB and the compliance mechanism, the aperture having a diameter in a first plane parallel to a major surface of the PCB, wherein a width of the probe region is fully disposed within the diameter of the aperture, wherein the width of the probe region is in a second plane parallel to the major surface of the PCB;
a plurality of wires coupled to the PCB, the plurality of wires extending from the PCB to the probe region, the plurality of wires disposed between the PCB and the probe region;
wire material of end portions of the plurality of wires comprising probe tips; and
an adhesive disposed in the aperture over and contacting a space transformer plate, wherein a sidewall of the aperture that is closest to the adhesive does not contact the adhesive, the sidewall of the aperture extending from the space transformer plate to the fix ring.

2. The test structure according to claim 1 , wherein the compliance mechanism comprises an elastomer plate.

3. The test structure according to claim 1 , wherein the compliance mechanism comprises at least one spring member.

4. The test structure according to claim 3 , wherein the at least one spring member comprises a constant pitch, a variable pitch, a cylindrical shape, a conical shape, an hourglass shape, a barrel shape, or a combination thereof.

5. The test structure according to claim 1 , wherein the compliance mechanism comprises a stiffness controllable frame structure.

6. The test structure according to claim 1 , further comprising a micro-electromechanical system (MEMS) rigid probe device coupled to the probe tips.

7. The test structure according to claim 6 , further comprising an interposer disposed between the MEMS rigid probe device and the probe tips.

8. The test structure according to claim 7 , wherein the compliance mechanism provides a first amount of compliance for the test structure and wherein the interposer provides a second amount of compliance for the test structure.

9. The test structure according to claim 1 , further comprising an interposer coupled to the probe tips.

10. The test structure according to claim 9 , wherein the interposer comprises a pliable material layer and a plurality of conductive springs disposed within the pliable material layer.

11. The test structure according to claim 10 , wherein the compliance mechanism provides a first amount of compliance for the test structure and wherein the interposer provides a second amount of compliance for the test structure.

12. The test structure according to claim 1 , wherein the plurality of wires extend through the aperture and the adhesive.

13. The test structure according to claim 1 , further comprising a metal plate disposed between the compliance mechanism and the PCB.

14. A test structure for semiconductor devices, the test structure comprising:
a space transformer (ST) plate;
a first plate coupled to the ST plate;
a second plate proximate to the first plate, wherein the first plate is disposed between the second plate and the ST plate;
a compliance mechanism disposed between the first plate and the second plate;
a printed circuit board (PCB) coupled to the second plate, wherein the second plate is disposed between the PCB and the compliance mechanism, and wherein an outer edge of the ST plate is fixedly attached to the PCB through through-holes in the first plate, the second plate, and the compliance mechanism, wherein a virtual straight line that extends from the ST plate to the PCB sequentially passes through the ST plate, the first plate, the compliance mechanism, the second plate, and the PCB;
a plurality of wires coupled between the PCB and the ST plate, the plurality of wires extending over a side of the PCB facing away from the ST plate and through an aperture extending through the PCB, the second plate, the compliance mechanism, and the first plate, the plurality of wires further extending through the ST plate;
a probe region proximate to ends of the plurality of wires, wherein wire material of end portions of the plurality of wires proximate to the probe region comprises probe tips, and wherein wire material of end portions of the plurality of wires proximate to the probe region are adapted to make electrical contact with contacts of a semiconductor device for testing; and
an adhesive disposed within the aperture and contacting a surface of the ST plate, wherein the adhesive does not contact a sidewall of the aperture, the sidewall of the aperture sequentially extending from the ST plate, along a sidewall of the first plate, along a sidewall of the compliance mechanism, and along a sidewall of the second plate.

15. The test structure according to claim 14 , further comprising a plurality of guide pins coupled to the ST plate and extending through through-holes in the first plate, the compliance mechanism, and the second plate.

16. The test structure according to claim 14 , wherein all surfaces of the PCB, the second plate, the compliance mechanism, and the first plate are free from the adhesive.

17. The test structure according to claim 14 , further comprising a micro-electromechanical system (MEMS) rigid probe device coupled to the probe tips.

18. A method of testing a semiconductor device, the method comprising:
providing a test structure, the test structure comprising a printed circuit board (PCB), a probe region, a compliance mechanism disposed between the PCB and the probe region, a space transformer (ST) plate disposed between the probe region and the compliance mechanism, a first metal plate disposed between the compliance mechanism and the PCB, a second metal plate disposed between the ST plate and the compliance mechanism, the PCB and the compliance mechanism fixedly attached to the ST plate by attachment elements extending through the PCB and the compliance mechanism, and a plurality of wires coupled between the PCB and the probe region, wherein the plurality of wires extends above a surface of the PCB facing away from the compliance mechanism and through an aperture extending completely through the PCB and the compliance mechanism, the plurality of wires further extending through a region of the ST plate, wherein wire material of end portions of the plurality of wires proximate the probe region comprise probe tips, wherein an adhesive is disposed in the aperture contacting the ST plate, wherein the adhesive does not contact a sidewall of the aperture, the sidewall of the aperture sequentially extending from the ST plate, along a sidewall of the first metal plate, along a sidewall of the compliance mechanism, and along a sidewall of the second metal plate;
providing a semiconductor device, the semiconductor device comprising contacts;
connecting wire material of end portions of the plurality of wires proximate the probe region to the contacts of the semiconductor device; and
testing the semiconductor device, wherein the compliance mechanism provides compliance in a direction substantially perpendicular to the semiconductor device while connecting the probe tips of the test structure to the contacts of the semiconductor device and while testing the semiconductor device.

19. The method according to claim 18 , wherein testing the semiconductor device comprises testing a single die of a semiconductor wafer, before or after singulating a pl

Assignees

• Kuo Yung Hsin
• Hung Wensen
• Yao Po Shi
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kuo Yung Hsin
• Hung Wensen
• Yao Po Shi

Classifications

• G01R31/2889 Primary

  Interfaces, e.g. between probe and tester (G01R31/31905 and G01R1/07364 take precedence) · CPC title

• G01R1/07371

  using an intermediate card or back card with apertures through which the probes pass · CPC title

• G01R31/303

  of integrated circuits (G01R31/305 - G01R31/315 take precedence) · CPC title

• G01R1/067 Primary

  Measuring probes · CPC title