Passive electrical devices with a polymer carrier

Patent metadata

Field	Value
Publication number	US-9888577-B2
Application number	US-201414229476-A
Country	US
Kind code	B2
Filing date	Mar 28, 2014
Priority date	Mar 28, 2014
Publication date	Feb 6, 2018
Grant date	Feb 6, 2018

Abstract

Passive electrical devices are described with a polymer carrier. In one example, a conductive layer is formed over a polymer substrate in a pattern to form a passive electrical device and at least two terminals of the device. A plurality of external connection pads are connected to the terminals of the device.

First claim

What is claimed is:

1. An Apparatus with a passive electrical device on a polymer substrate comprising:
a polymer substrate formed over a plurality of electrical devices, wherein the electrical devices have one or more exposed pads;
a dielectric layer formed over the polymer substrate and the exposed pads, wherein the dielectric layer is patterned to form one or more via openings over the exposed pads;
a conductive layer over the polymer substrate, the dielectric layer, and the one or more via openings to form one or more vias, wherein the conductive layer is patterned to form a passive electrical device and at least two terminals of the device that are electrically coupled to the one or more vias to form one or more circuits with the electrical devices of the polymer substrate;
a dielectric solder stop layer over the conductive layer;
a plurality of external connection pads as solder balls over the solder stop layer for connection to a package substrate and over the conductive layer connected to the terminals of the device; and
the package substrate attached to the external connection pads of the polymer substrate on one side and having a ball grid array on an opposite side to attach to a printed circuit board.

2. The apparatus of claim 1 , wherein the polymer substrate is formed by compression molding a filled mold material onto a temporary carrier and releasing the temporary carrier.

3. The apparatus of claim 1 , wherein the conductive layer comprises a redistribution layer formed on the polymer substrate.

4. The apparatus of claim 1 , wherein the pattern ids a plurality of coils that is tunable by disconnecting one of the coils from the plurality of coils.

5. The apparatus of claim 1 , wherein the pattern is a plurality of coils that is tunable by short circuiting a portion of one of the coils to a terminal of the passive electrical device.

6. The apparatus of claim 1 , further comprising a dielectric layer over the conductive layer and a second conductive layer in a pattern to form a second passive electrical device and at least two terminals of the second device over the dielectric layer.

7. The apparatus of claim 1 , further comprising a passive electrical component embedded in the polymer substrate and external connectors extending to the conductive layer to externally connect the embedded passive electrical component.

8. The apparatus of claim 1 , wherein the passive electrical device comprises a tunable feature that is an additional portion of a coil that may be disconnected by removing a portion of the patterned conductive layer.

9. The apparatus of claim 1 , wherein the passive electrical device comprises a tunable feature that is a portion of the passive electronic device that can be trimmed.

10. The apparatus of claim 1 , further comprising an additional passive electrical device attached to the substrate on a side opposite the dielectric solder stop layer and coupled to a connection pad by a via through the substrate.

11. A method of forming a passive electrical device on a polymer substrate comprising:
forming a polymer substrate over a plurality of electrical devices, wherein the electrical devices have one or more exposed pads;
forming a dielectric layer over the polymer substrate and the exposed pads, wherein the dielectric layer is patterned to form one or more via openings over the exposed pads;
forming a conductive layer over the polymer substrate, the dielectric layer, and the one or more via openings to form one or more vias, wherein the conductive layer is patterned to form a passive electrical device;
forming the conductive layer to form at least two terminals of the device that are electrically coupled to the one or more vias to form one or more circuits with the electrical devices of the polymer substrate;
forming a dielectric solder stop layer over the conductive layer;
forming a plurality of external connection pads a solder balls over the solder stop layer for connection to a package substrate over the conductive layer connected to the terminals of the device; and
attaching the external connection pads to the package substrate, the package substrate having a ball grid array opposite the polymer substrate to attach to a printed circuit board.

12. The method of claim 11 , further comprising forming a dielectric layer over the passive electrical device and wherein forming the external connection pads comprises forming the pads over the dielectric layer.

13. The method of claim 11 , further comprising pressing a mold compound filled with one or more of aluminum oxide, or silica over a temporary substrate and releasing the temporary substrate to form the polymer substrate.

14. The method of claim 13 , further comprising placing a passive electrical component on the temporary carrier before pressing the mold compound to embed the component in the polymer substrate.

15. The method of claim 11 , wherein forming the conductive layer comprises depositing a metal and then performing patterned etching.

16. The method of claim 11 , further comprising forming a dielectric layer over the conductive layer and forming a second conductive layer in a pattern to form a second passive electrical device and at least two terminals of the second device over the dielectric layer.

17. The method of claim 11 , further comprising tuning the passive electrical device.

18. A computing system comprising:
a communication chip for communication of data to and from the computing system;
a processor;
a printed circuit board to connect the communication chip and the processor; and
integrated passive devices over a polymer substrate, wherein the integrated passive devices have one or more exposed pads, wherein a dielectric layer is formed over the polymer substrate and the exposed pads, wherein the dielectric layer is patterned to form one or more via openings over the exposed pads, wherein there is a conductive layer over the polymer substrate, the dielectric layer, and the one or more via openings to form one or more vias, wherein the conductive layer is patterned to form a passive electrical device and at least two terminals of the device that are electrically coupled to the one or more vias to form one or more circuits with the electrical devices of the polymer substrate, a dielectric solder stop layer over the conductive layer, a plurality of external connection pads as solder balls over the solder stop layer for connection to a package substrate and over the conductive layer connected to the terminals of the device, and the package substrate attached to the external connection pads of the polymer substrate on one side and having a ball grid array on an opposite side to attach to the printed circuit board.

19. The computing device of claim 18 , wherein the conductive layer comprises a redistribution layer formed on the polymer substrate.

20. The apparatus claim 18 , wherein the pattern is a plurality of coils that are tunable by short circuiting a portion of one coils to a terminal of the passive electrical device.

Assignees

• Intel Corp

Inventors

• Meyer Thorsten
• Ofner Gerald
• Albers Sven
• Mahnkopf Reinhard

Classifications

• H05K2201/10636

  Leadless chip, e.g. chip capacitor or resistor · CPC title

• H05K1/162

  incorporating printed capacitors · CPC title

• H05K1/0233

  Filters, inductors or a magnetic substance · CPC title

• H05K1/165

  incorporating printed inductors · CPC title

• H05K2203/1469

  Circuit made after mounting or encapsulation of the components · CPC title