Semiconductor device

Patent metadata

Field	Value
Publication number	US-9887293-B2
Application number	US-201615191542-A
Country	US
Kind code	B2
Filing date	Jun 24, 2016
Priority date	May 20, 2016
Publication date	Feb 6, 2018
Grant date	Feb 6, 2018

Abstract

A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a dielectric layer, a first gate electrode, a second gate electrode and a charge storage structure. The oxide-semiconductor layer is disposed on the first gate electrode on the substrate. The source/drain regions are disposed on the oxide-semiconductor layer. The first dielectric layer covers on the oxide-semiconductor layer and source/drain regions. A second gate electrode is disposed between source/drain regions and partially covers the oxide-semiconductor layer. The oxide-semiconductor layer may be optionally disposed between the first gate electrode and the oxide-semiconductor layer or be disposed on the second gate electrode.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
an oxide-semiconductor layer on a first gate electrode on said substrate;
two source/drain regions on said oxide-semiconductor layer;
a first dielectric layer covering on said oxide-semiconductor layer and said two source/drain regions;
a second gate electrode between said two source/drain regions and partially covering said oxide-semiconductor layer; and
a charge storage structure on said second gate electrode.

2. The semiconductor device of claim 1 , further comprising:
a sealing layer on said substrate and covering the sidewall of said charge storage structure.

3. The semiconductor device of claim 2 , wherein said sealing layer covers said oxide-semiconductor layer, said two source/drain regions, said charge storage structure and said second gate electrode.

4. The semiconductor device of claim 2 , wherein said sealing layer comprises a dielectric material.

5. The semiconductor device of claim 1 , wherein said charge storage structure comprises an oxide-nitride-oxide structure.

6. The semiconductor device of claim 1 , wherein said charge storage structure comprises a floating gate.

7. The semiconductor device of claim 6 , further comprising:
a second dielectric layer between said second gate electrode and said floating gate.

8. The semiconductor device of claim 6 , wherein said floating gate covers said first gate electrode in a projection direction.

9. The semiconductor device of claim 6 , further comprising:
a conductive layer on said floating gate.

10. The semiconductor device of claim 9 , wherein said conductive layer is provided with a conductive material different from the material of said second gate electrode.

Assignees

• United Microelectronics Corp

Inventors

• Zhou Zhibiao
• Chen Ding Lung
• Lin chen bin
• Wang Sanpo
• Lee Chung Yuan
• Ku Chi Fa

Classifications

• H10D30/6734

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title

• H01L29/78648

  Electricity · mapped topic

• H01L29/788

  Electricity · mapped topic

• H01L29/78609 Primary

  Electricity · mapped topic

• H01L29/7869

  Electricity · mapped topic