Process method and structure for high voltage MOSFETs

Patent metadata

Field	Value
Publication number	US-9887283-B2
Application number	US-201313892191-A
Country	US
Kind code	B2
Filing date	May 10, 2013
Priority date	May 10, 2013
Publication date	Feb 6, 2018
Grant date	Feb 6, 2018

Abstract

This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches each having a trench endpoint with an endpoint sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the endpoint sidewall wherein the sidewall dopant region extends vertically downward along the endpoint sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.

First claim

We claim:

1. A semiconductor power device disposed in a semiconductor substrate comprising:
a plurality of trenches formed at a top portion of the semiconductor substrate and extending along a longitudinal direction each of the trenches having a trench endpoint with an endpoint sidewall perpendicular to the longitudinal direction and extends vertically downward from a top surface to a trench bottom surface wherein at least two of the trench endpoints with respective endpoint sidewalls are disposed adjacent to each other;
a trench bottom body dopant region disposed in the semiconductor substrate immediately below the trench bottom surface with a laterally extended region extending laterally beyond the trench bottom surface; and
at least two endpoint sidewall body dopant regions disposed in the semiconductor substrate along at least two of the endpoint sidewalls that constitute adjacent endpoint sidewall body dopant region configured by two of the trenches disposed immediately adjacent to each other wherein the adjacent endpoint sidewall body dopant regions extend through an entire semiconductor region between the at least two of the endpoint sidewalls that are disposed adjacent to each other having a substantially uniform lateral width from the endpoint sidewall and wherein the adjacent endpoint sidewall body dopant regions further merged into a joined endpoint sidewall body dopant region and extends vertically downward along an entire length of the endpoint sidewall of the trench to reach and directly contact the laterally extended region of the trench bottom body dopant region.

2. The semiconductor power device of claim 1 wherein:
each of the plurality of trenches is padded with an insulation layer covering sidewalls and the trench bottom surface.

3. The semiconductor power device of claim 1 wherein:
each of the plurality of trenches is padded with an insulation layer covering sidewalls and the trench bottom surface wherein the insulation layer covering the sidewalls and the trench bottom surface having approximately a same thickness.

4. The semiconductor power device of claim 1 wherein:
each of the plurality of trenches is padded with an insulation layer covering sidewalls and the trench bottom surface wherein the insulation layer covering the endpoint and the non-endpoint sidewalls having a smaller layer thickness than the insulation layer covering the trench bottom surface.

5. The semiconductor power device of claim 1 wherein:
each of the plurality of trenches is configured to extend between two designated locations and wherein the trenches have different lengths, wherein the trench endpoints are distributed at designated locations on the entire area of the semiconductor substrate.

6. The semiconductor power device of claim 1 further comprising:
a high voltage (HV) MOSFET device.

7. The semiconductor power device of claim 1 further comprising:
a high voltage (HV) IGBT device.

Assignees

• Ding Yongping
• Zhang Lei
• Chang Hong
• Kim Jongoh
• Chen John
• Alpha & Omega Semiconductor

Inventors

• Ding Yongping
• Zhang Lei
• Chang Hong
• Kim Jongoh
• Chen John

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/212

  Through-implantation · CPC title

• H10P30/204 Primary

  into Group IV semiconductors · CPC title

• H01L29/78 Primary

  Electricity · mapped topic

• H01L29/66348

  Electricity · mapped topic