Charge compensation device and manufacturing therefor

Patent metadata

Field	Value
Publication number	US-9887261-B2
Application number	US-201615264729-A
Country	US
Kind code	B2
Filing date	Sep 14, 2016
Priority date	Jul 1, 2014
Publication date	Feb 6, 2018
Grant date	Feb 6, 2018

Abstract

A charge-compensation semiconductor device includes a semiconductor body having a first surface, a lateral edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, an active area, and a peripheral area arranged between the active area and the lateral edge. A source metallization is arranged on the first surface. A drain metallization is arranged opposite to the source metallization. The semiconductor body further includes a drift region in Ohmic contact with the drain metallization, and a plurality of compensation regions forming respective pn-junctions with the drift region, which are arranged in the active area and in the peripheral area, and are in Ohmic contact with the source metallization via respective body regions arranged in the active area and having a higher doping concentration than the compensation regions. In a horizontal cross-section substantially parallel to the first surface the compensation regions are at least in a respective portion shaped as a strip oriented in a direction which is tilted with respect to the lateral edge by a tilt angle.

First claim

The invention claimed is:

1. A method for manufacturing a charge-compensation semiconductor device, the method comprising:
providing a wafer comprising a first surface and a drift region of a first conductivity type extending to the first surface;
defining active device areas each of which is surrounded by a respective peripheral device area;
forming a mask on the first surface, when seen from above the mask comprising strip-shaped openings which are substantially parallel to each other and extend from one the active device areas into the respective peripheral device area or v-shaped openings extending from the active device area into the respective peripheral device area;
forming compensation regions of a second conductivity type, comprising at least one of:
etching trenches from the first surface into the drift region using the mask so that each trench comprises a sidewall which has a depth that extends substantially perpendicular to the first surface, and wherein each trench extends longitudinally through the drift region in a direction parallel to the first surface;
filing the trenches with a semiconductor material of the second conductivity type comprising epitaxial depositing; and
implanting dopants of the second conductivity type into the drift region using the mask as an implantation mask to form the compensation regions having a depth that extend substantially perpendicular to the first surface and extend longitudinally through the drift region in a direction parallel to the first surface;

forming a source metallization on the first surface in Ohmic contact with the compensation regions;
forming a drain metallization opposite to the source metallization and in Ohmic contact with the drift region;
separating the wafer into individual charge-compensation semiconductor devices, so that at least one of the charge-compensation semiconductor devices comprises a lateral edge which delimits the charge-compensation semiconductor device in a horizontal direction substantially parallel to the first surface and forms an acute angle with the longitudinal direction of the trenches or the implanted compensation regions.

2. The method of claim 1 , further comprising implanting doping ions into portions of the compensation regions which are arranged in the active area of the at least one charge-compensation semiconductor device and next to the first surface.

3. The method of claim 1 , further comprising forming in the peripheral device area of the at least one charge-compensation semiconductor device and on the first surface a conductive drain ring in Ohmic contact with the drain metallization.

4. The method of claim 3 , further comprising forming in the peripheral device area of the at least one charge-compensation semiconductor device and on the first surface a conductive gate ring arranged between the conductive drain ring and the active device area of the at least one charge-compensation semiconductor device.

5. The method of claim 1 , further comprising at least one of implanting ions into the active area of the at least one charge-compensation semiconductor device; and forming a plurality of insulated gate electrodes next to the first surface in the active area of the at least one charge-compensation semiconductor device.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Weber Hans
• Tutuc Daniel
• Voerckel Andreas

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title

• H10P30/21

  of electrically active species · CPC title