Vertical semiconductor device
US-2017194347-A1 · Jul 6, 2017 · US
Vertical memory device
US9887208B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9887208-B2 |
| Application number | US-201615218421-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 25, 2016 |
| Priority date | Nov 10, 2015 |
| Publication date | Feb 6, 2018 |
| Grant date | Feb 6, 2018 |
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- Title
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Abstract
Official abstract text for this publication.
A memory device may include a peripheral region and a cell region. The peripheral region may include a first substrate, a plurality of circuit elements disposed on the first substrate, a first insulating layer disposed on the plurality of circuit elements, and a first protective layer disposed in the first insulating layer. The cell region may include a second substrate disposed on the first insulating layer, wherein the cell region includes a first impurity region, a channel region extending in a direction substantially perpendicular to an upper surface of the second substrate, a plurality of gate electrode layers stacked on the second substrate and adjacent to the channel region, and a first contact electrically connected to the first impurity region, wherein the first protective layer is disposed below the first impurity region, and has a shape corresponding to a shape of the first impurity region.
First claim
Opening claim text (preview).
What is claimed is: 1. A memory device, comprising: a peripheral region including a first substrate, a plurality of circuit elements disposed on the first substrate, a first insulating layer disposed on the plurality of circuit elements, and a first protective layer disposed in the first insulating layer; and a cell region including a second substrate disposed on the first insulating layer, wherein the cell region includes a first impurity region, a channel region extending in a direction substantially perpendicular to an upper surface of the second substrate, a plurality of gate electrode layers stacked on the second substrate and adjacent to the channel region, and a first contact electrically connected to the first impurity region, wherein the first protective layer is disposed below the first impurity region, and has a shape corresponding to a shape of the first impurity region. 2. The memory device of claim 1 , wherein the first contact passes through the second substrate in the first impurity region. 3. The memory device of claim 2 , wherein the first contact passes through the second substrate and is connected to the first protective layer. 4. The memory device of claim 1 , wherein the peripheral region is connected to the plurality of circuit elements, and includes a plurality of wiring patterns disposed in the first insulating layer. 5. The memory device of claim 4 , wherein the first protective layer is isolated from the plurality of wiring patterns in the first insulating layer. 6. The memory device of claim 4 , wherein the first protective layer is connected to at least one of the plurality of circuit elements and at least one of the plurality of wiring patterns in the first insulating layer. 7. The memory device of claim 4 , wherein the first protective layer and the plurality of wiring patterns include the same material. 8. The memory device of claim 1 , wherein the cell region includes a barrier layer disposed between the first contact and the first impurity region. 9. The memory device of claim 1 , wherein the second substrate includes a second impurity region disposed below a common source line dividing the plurality of gate electrode layers and the channel region into a plurality of regions, and the first impurity region and the second impurity region include different conductive impurities, respectively. 10. The memory device of claim 1 , wherein the first substrate includes a monocystalline silicon, and the second substrate includes a polycrystalline silicon. 11. The memory device of claim 1 , wherein the cell region includes a plurality of second contacts disposed between the channel region and the first contact, and wherein each of the plurality of second contacts is connected to a respective one of the plurality of gate electrode layers.
Assignees
Inventors
Classifications
Sensing or reading circuits; Data output circuits · CPC title
Programming or data input circuits · CPC title
Electricity · mapped topic
- H01L27/11582Primary
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9887208B2 cover?
- A memory device may include a peripheral region and a cell region. The peripheral region may include a first substrate, a plurality of circuit elements disposed on the first substrate, a first insulating layer disposed on the plurality of circuit elements, and a first protective layer disposed in the first insulating layer. The cell region may include a second substrate disposed on the first in…
- Who is the assignee on this patent?
- Son Young Hwan, Park Young Woo, Lee Jae Duk, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification H01L27/11582. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 06 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).