Multiple metal layer semiconductor device and low temperature stacking method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9887155-B2
Application number	US-201213651045-A
Country	US
Kind code	B2
Filing date	Oct 12, 2012
Priority date	Sep 28, 2012
Publication date	Feb 6, 2018
Grant date	Feb 6, 2018

Abstract

A semiconductor device including a conductive element and an interface surface fabricated atop the conductive element, and a method for fabricating such a device are described. An exemplary device includes a substrate having a conductive element and a metal layer fabricated atop the conductive element. An oxide layer is fabricated atop the metal layer, thus forming an interface surface. During polishing (e.g., planarization), in which an upper portion of the interface surface is removed, the presence of the interface surface greatly reduces the loading on the conductive element. A second substrate fabricated using the same process may be stacked atop the first substrate and bonded using a hybrid bonding process.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
providing a first substrate having a first conductive element disposed therein;
forming a first insulator layer over the first substrate;
removing a portion of the first insulator layer to expose the first conductive element;
forming a first metal layer on the exposed first conductive element;
polishing the first insulator layer and the first metal layer, thereby planarizing a top surface of the first substrate, wherein the polished first metal layer comprises a first surface in contact with the first conductive element and a second surface away from the first conductive element, wherein the first surface has a first width along a first direction parallel to a top surface of the first substrate and the second surface has a second width along the first direction, wherein the second width is larger than the first width;
providing a second substrate having a second conductive element disposed therein;
forming a second insulator layer over the second substrate;
removing a portion of the second insulator layer to expose the second conductive element;
forming a second metal layer on the exposed second conductive element;
polishing the second insulator layer and the second metal layer, thereby planarizing a top surface of the second substrate, wherein the polished second metal layer comprises a third surface in contact with the second conductive element and a fourth surface away from the second conductive element, wherein the third surface has a third width along a second direction parallel to a top surface of the second substrate and the fourth surface has a fourth width along the second direction, wherein the fourth width is larger than the third width; and
bonding the first substrate to the second substrate such that the first metal layer and the second metal layer are substantially aligned and in contact, and the first insulator layer and the second insulator layer are in contact.

2. The method of claim 1 , wherein the fourth width is equal to the second width.

3. The method of claim 2 , wherein the bonding the first substrate to the second substrates is performed such the first direction and the second direction are substantially aligned.

4. The method of claim 1 , wherein the bonding the first substrate to the second substrates includes:
bonding the first metal layer to the second metal layer with a eutectic bond; and
bonding the first insulator layer to the second insulator layer with a fusion bond.

5. The method of claim 1 , wherein the first and second metal layers are of the same material.

6. The method of claim 1 , wherein the first and second metal layers are of different materials.

7. The method of claim 1 , wherein the forming the first metal layer on the exposed first conductive element and the forming the second metal layer on the exposed second conductive element are performed by a method selected from a group consisting of electroplating, electroless plating, and physical vapor deposition.

8. The method of claim 1 , wherein the first and second insulator layers comprise silicon oxide.

9. The method of claim 1 , wherein the first and second conductive elements are of a first material, and wherein the first and second metal layers are of a second material different from the first material.

10. A method of fabricating a semiconductor device, the method comprising:
providing a first substrate having a first conductive element disposed therein, the first conductive element including a top surface, the top surface of the first conductive element having a first width along a first direction;
forming a first oxide layer over the first substrate;
removing a portion of the first oxide layer to expose the top surface of the first conductive element;
forming a first metal layer atop the exposed top surface of the first conductive element;
polishing the first oxide layer and the first metal layer, wherein the polished first metal layer comprises a first surface in contact with the top surface of first conductive element and a second surface away from the top surface of the first conductive element, wherein the first surface has a second width along the first direction and the second surface has a third width along the first direction;
providing a second substrate having a second conductive element disposed therein, the second conductive element including a top surface, the top surface of the second conductive element having a fourth width along a second direction;
forming a second oxide layer over the second substrate;
removing a portion of the second oxide layer to expose the top surface of the second conductive element;
forming a second metal layer atop the exposed top surface of the second conductive element;
polishing the second oxide layer and the second metal layer, wherein the polished second metal layer comprises a third surface in contact with the top surface of second conductive element and a fourth surface away from the top surface of the second conductive element, wherein the third surface has a fifth width along the second direction and the fourth surface has a sixth width along the second direction; and
bonding the first substrate to the second substrate such that the second surface of first metal layer and the fourth surface of the second metal layer are substantially aligned and in contact, and the first insulator layer and the second insulator layer are in contact, wherein the third width and the first width are larger than the second width, and the sixth width and fourth width are larger than the fifth width.

11. The method of claim 10 , wherein the third width is equal to the sixth width.

12. The method of claim 11 , wherein the bonding the first substrate to the second substrates is performed such the first direction and the second direction are substantially aligned.

13. The method of claim 10 , wherein the bonding the first substrate to the second substrates includes:
bonding the first metal layer to the second metal layer with a eutectic bond; and
bonding the first oxide layer to the second oxide layer with a fusion bond.

14. The method of claim 10 , wherein the first and second metal layers are of the same material.

15. The method of claim 10 , wherein the first and second metal layers are of different materials.

16. The method of claim 10 , wherein the forming the first metal layer on the exposed top surface of the first conductive element and the forming the second metal layer on the exposed top surface of the second conductive element are performed by a method selected from a group consisting of electroplating, electroless plating, and physical vapor deposition.

17. The method of claim 10 , wherein the bonding the first substrate to the second substrates is performed at a bonding temperature between room temperature and 100° C.

18. The method of claim 10 , wherein the first and second conductive elements are of a first material, and wherein the first and second metal layers are of a second material different from the first material.

19. A method of fabricating a semiconductor device, the method comprising:
providing a first substrate having a first conductive element disposed therein, the first conductive element including a top surface, the top surface having a first width along a first direction;
forming a first insulator layer over the first substrate;
removing a portion of the first insulator layer to expose the top surface of the first conductive element;
forming a first metal layer

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liu Ping Yin
• Cheng Kai Wen
• Huang Xin Hua
• Chao Lan Lin
• Tsai Chia Shiung
• Chen Xiaomeng

Classifications

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/40 Primary

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10P14/20

  of semiconductor materials · CPC title

• H10P95/00 Primary

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H01L21/7684

  Electricity · mapped topic