Biometric sensor chip having distributed sensor and control circuitry

Patent metadata

Field	Value
Publication number	US-9883822-B2
Application number	US-201615181229-A
Country	US
Kind code	B2
Filing date	Jun 13, 2016
Priority date	Jun 5, 2013
Publication date	Feb 6, 2018
Grant date	Feb 6, 2018

Abstract

A sensor includes a sensor array formed on a first side of a substrate and at least one circuit operative to communicate with the sensor array formed on a second side of the substrate. At least one via extends through the substrate to electrically connect the sensor array to the at least one circuit. Placing the at least one circuit on the second side of the substrate allows the sensor array to occupy substantially all of the first side of the substrate.

First claim

We claim:

1. A biometric sensor, comprising:
a capacitive sensor array configured to image biometric data and formed on a first side of a substrate, the sensor array comprising:
a first plurality of electrical traces defining a plurality of rows;
a second plurality of electrical traces defining a plurality of columns, the plurality of columns intersecting the plurality of rows, thereby defining a plurality of intersections; and
a capacitive sensing element formed at each of the plurality of intersections;

at least one circuit formed on a second opposing side of the substrate and configured to communicate with the sensor array; and
a plurality of vias extending through the substrate to electrically connect the sensor array to the at least one circuit; wherein
each of the plurality of vias underlies an electrical trace chosen from the first or the second plurality of electrical traces.

2. The biometric sensor of claim 1 , wherein the plurality of vias separates the sensor array into a plurality of sensor sub-arrays.

3. The biometric sensor of claim 2 , wherein each sensor sub-array in the plurality of sensor sub-arrays is separately addressable by the at least one circuit.

4. The biometric sensor of claim 2 , wherein at least one of the plurality of sensor sub-arrays comprises:
a subgroup of the plurality of rows; and
a subgroup of the plurality of columns, the subgroup of the plurality of columns intersecting the subgroup of the plurality of rows;
wherein an RC constant of the at least one of the plurality of sensor sub-arrays is less than an RC constant of the sensor array.

5. The biometric sensor of claim 2 , wherein the plurality of sub-arrays images a biometric parameter faster than the sensor array.

6. The biometric sensor of claim 1 , wherein the substrate electrically shields the at least one circuit from the capacitive sensor array.

7. A fingerprint sensor, comprising:
a sensor array comprising biometric sensing elements formed on a first side of a substrate, the sensor array comprising:
a first plurality of electrical traces defining a plurality of rows; and
a second plurality of electrical traces defining a plurality of columns, the plurality of columns intersecting the plurality of rows to define a plurality of intersections;
wherein a respective biometric sensing element is formed at each of the plurality of intersections and each biometric sensing element is configured to image a fingerprint;

at least one circuit formed on a second opposing side of the substrate and configured to communicate with the sensor array; and
a plurality of vias extending through the substrate to electrically connect the sensor array to the at least one circuit, wherein each of the plurality of vias is formed at a unique end of one of the plurality of rows and the plurality of columns.

8. The fingerprint sensor of claim 7 , wherein the substrate electrically shields the at least one circuit from the sensor array.

9. A fingerprint sensor, comprising:
a sensor array configured to capture fingerprint data and formed on a first side of a substrate, the sensor array comprising:
a first plurality of electrical traces defining a plurality of rows; and
a second plurality of electrical traces defining a plurality of columns, the plurality of columns intersecting the plurality of rows, thereby defining a plurality of intersections; and
a capacitive sensing element formed at each of the plurality of intersections;

at least one circuit formed on a second opposing side of the substrate and operative to communicate with the sensor array; and
a plurality of vias extending through the substrate to electrically connect the sensor array to the at least one circuit, wherein each of the plurality of vias underlies a trace chosen from the first or second plurality of traces.

10. The fingerprint sensor of claim 9 , wherein the plurality of vias separates the sensor array into a plurality of sensor sub-arrays.

11. The fingerprint sensor of claim 10 , wherein each sensor sub-array in the plurality of sensor sub-arrays is separately addressable by the at least one circuit.

12. The fingerprint sensor of claim 10 , wherein at least one of the plurality of sensor sub-arrays comprises:
a subgroup of the plurality of rows; and
a subgroup of the plurality of columns, the subgroup of the plurality of columns intersecting the subgroup of the plurality of rows;
wherein an RC constant of the at least one of the plurality of sensor sub-arrays is less than an RC constant of the sensor array.

13. The fingerprint sensor of claim 10 , wherein the plurality of sub-arrays images a biometric parameter faster than the sensor array.

14. The fingerprint sensor of claim 9 , wherein the substrate electrically shields the at least one circuit from the sensor array.

15. An electronic device, comprising:
a cover layer; and
a fingerprint sensor positioned below the cover layer, the fingerprint sensor comprising:
a sensor array configured to image fingerprint data and formed on a first side of a substrate, the sensor array comprising:
a first plurality of electrical traces defining a plurality of rows;
a second plurality of electrical traces defining a plurality of columns, the plurality of columns intersecting the plurality of rows to define a plurality of intersections; and
a capacitive sensing element formed at each of the plurality of intersections;

at least one circuit formed on a second opposing side of the substrate and operative to communicate with the sensor array; and
a plurality of vias extending through the substrate to electrically connect the sensor array to the at least one circuit; wherein
each of the plurality of vias underlies an electrical trace chosen from the first or the second plurality of electrical traces; or
each of the plurality of vias is formed at a unique end of one of the plurality of rows and the plurality of columns.

16. The electronic device of claim 15 , wherein the substrate electrically shields the at least one circuit from the sensor array.

Assignees

• Apple Inc

Inventors

• Bhagavat Milind S
• Zhai Jun

Classifications

• A61B2562/0214

  Capacitive electrodes · CPC title

• G06K9/0002

  Physics · mapped topic

• H01L27/14634

  Electricity · mapped topic

• A61B5/053

  Measuring electrical impedance or conductance of a portion of the body · CPC title

• A61B2562/182

  Electrical shielding, e.g. using a Faraday cage · CPC title