Semiconductor device with a tunneling layer having a varying nitrogen concentration, and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9882018-B2
Application number	US-201514713039-A
Country	US
Kind code	B2
Filing date	May 15, 2015
Priority date	Aug 6, 2014
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

A semiconductor device includes: a substrate including a channel region; a gate dielectric a tunneling layer, a charge storage layer, and a blocking layer sequentially disposed on the channel region; and a gate electrode disposed on the gate dielectric, wherein the tunneling layer has variations in nitrogen concentrations in a direction perpendicular to the channel region, and has a maximum nitrogen concentration in a position shifted from a center of the tunneling layer toward the charge storage layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a channel region;
a gate dielectric including a tunneling layer, a charge storage layer and a blocking layer disposed on a surface of the channel region in the foregoing order such that the tunneling layer abuts the surface of the channel region; and
a gate electrode disposed on the gate dielectric,
wherein the tunneling layer comprises nitrogen throughout,
the nitrogen concentration of the tunneling layer varies along an axis normal to the surface of the channel region, and
the nitrogen concentration of the tunneling layer is maximum only at a location offset from a center of the tunneling layer, in a direction along the axis toward the charge storage layer wherein the tunneling layer has a first region, a second region, and a third region disposed in the foregoing order in a direction along said axis from the charge storage layer, the second region has a higher nitrogen concentration than each of the first and third regions, and the third region of the tunneling layer includes the center of the tunneling layer.

2. The semiconductor device of claim 1 , wherein the nitrogen concentration increases from the first region to the second region and decreases in the third region in said direction.

3. The semiconductor device of claim 1 , wherein the nitrogen concentration of the second region ranges from 22 atomic percent to 28 atomic percent.

4. The semiconductor device of claim 1 , wherein the tunneling layer also has a fourth region in contact with the third region, and a fifth region in contact with the fourth region and with a nitrogen concentration different from that of the fourth region.

5. The semiconductor device of claim 4 , wherein the nitrogen concentration of each of the fourth region and the fifth region is lower than that of the third region.

6. The semiconductor device of claim 4 , wherein the nitrogen concentration of the fifth region is lower than that of the fourth region.

7. The semiconductor device of claim 4 , wherein the third region is thicker than any of the other said regions of the tunneling layer.

8. The semiconductor device of claim 1 , wherein the maximum nitrogen concentration of the tunneling layer ranges from 25 atomic percent to 30 atomic percent.

9. The semiconductor device of claim 1 , wherein the tunneling layer has a surface that contacts the charge storage layer, and
the maximum nitrogen concentration is located at a distance equal to 25% to 40% of the thickness of the tunneling layer in said direction from a surface of the tunneling layer that contacts the charge storage layer.

10. A semiconductor device, comprising:
a stack of gate electrodes and interlayer insulating layers on a substrate, wherein the gate electrodes are disposed alternately with the interlayer insulating layers in the stack;
channel regions extending through the stack; and
a gate dielectric including a tunneling layer, a charge storage layer, and a blocking layer stacked in the foregoing order around a vertical surface of each of the channel regions such that the tunneling layer abuts the surface of each of the channel regions, and
wherein the tunneling layer of the gate dielectric comprises nitrogen throughout,
the nitrogen concentration of the tunneling layer varies along an axis normal to the vertical surface of the channel region, and
the nitrogen concentration of the tunneling layer is maximum only at a location offset from a center of the tunneling layer, along said axis, toward the charge storage layer wherein the tunneling layer has a first region, a second region, and a third region disposed in the foregoing order in a direction along said axis from the charge storage layer, the second region has a higher nitrogen concentration than each of the first and third regions, and the third region of the tunneling layer includes the center of the tunneling layer.

11. The semiconductor device of claim 10 , wherein the nitrogen concentration of the tunneling layer increases and then decreases in a direction along said axis from the charge storage layer to the channel region.

12. A semiconductor device, comprising:
a channel region of semiconductor material;
a gate electrode; and
a tunneling layer, a charge storage layer and a blocking layer collectively interposed between a surface of the channel region and the gate electrode,
wherein the tunneling layer abuts the channel region and is interposed between the charge storage layer and the channel region, and the blocking layer is interposed between the charge storage layer and the gate electrode,
the tunneling layer comprises nitrogen throughout,
the nitrogen concentration of the tunneling layer varies substantially in a direction from the charge storage layer to the channel region, and
the nitrogen concentration of the tunneling layer is maximum only at a location in the tunneling layer between a center of the tunneling layer and the charge storage layer wherein the tunneling layer has a first region, a second region, and a third region disposed in the foregoing order in a direction along said axis from the charge storage layer, the second region has a higher nitrogen concentration than each of the first and third regions, and the third region of the tunneling layer includes the center of the tunneling layer.

13. The semiconductor device of claim 12 ,
wherein the nitrogen concentration of the tunneling layer has one region in which the nitrogen concentration thereof increases towards said location, and another region in which the nitrogen concentration thereof decreases away from said location.

14. The semiconductor device of claim 13 ,
wherein said tunneling layer has a surface contacting the charge storage layer, and said location at which the nitrogen concentration of the tunneling layer is maximum is spaced by a distance equal to 25% to 40% of a thickness of the tunneling layer from the surface of the tunneling layer contacting the charge storage layer.

15. The semiconductor device of claim 12 ,
wherein the nitrogen concentration of the tunneling layer at said location is within a range of 25 atomic percent to 30 atomic percent.

16. The semiconductor device of claim 1 , wherein the tunneling layer directly contacts the charge storage layer.

17. The semiconductor device of claim 10 , wherein the tunneling layer directly contacts the charge storage layer.

18. The semiconductor device of claim 12 , wherein the tunneling layer directly contacts the charge storage layer.

Assignees

• Noh Young Jin
• Choi Jae Ho
• Kim Bio
• Park Kwang Min
• Ahn Jae Young
• Yoo Dong Chul
• Lim Seung Hyun
• Lee Jeon Il
• Samsung Electronics Co Ltd

Inventors

• Noh Young Jin
• Choi Jae Ho
• Kim Bio
• Park Kwang Min
• Ahn Jae Young
• Yoo Dong Chul
• Lim Seung Hyun
• Lee Jeon Il

Classifications

• H01L27/11582

  Electricity · mapped topic

• H01L29/7883

  Electricity · mapped topic

• H01L29/792

  Electricity · mapped topic

• H01L29/518 Primary

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic