Pixel circuit

Patent metadata

Field	Value
Publication number	US-9881968-B2
Application number	US-201614988376-A
Country	US
Kind code	B2
Filing date	Jan 5, 2016
Priority date	Aug 9, 2013
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

A pixel arrangement includes a photodiode, a reset transistor configured to be controlled by a reset signal and coupled to a reset input voltage, a transfer gate transistor configured to transfer charge from the photodiode to a node, wherein the transfer gate transistor is controlled by a transfer gate voltage, and a source follower transistor controlled by the voltage on the node and coupled to a source follower voltage. A capacitor is coupled between the node and an input voltage. During a read operation the input voltage is increased to boost the voltage at the node. The increased input voltage may, for example, be one the reset input voltage, said source follower voltage, said transfer gate voltage and a boosting voltage.

First claim

What is claimed is:

1. A pixel arrangement, comprising:
a photodiode;
a reset transistor configured to be controlled by a reset signal and coupled to a reset input voltage;
a transfer gate transistor configured to transfer charge from the photodiode to a node, said transfer gate transistor configured to be controlled by a transfer gate voltage;
a source follower transistor configured to be controlled by the voltage on the node;
a pass transistor configured to be controlled by a pass control signal; and
a capacitor having a first plate connected to the node and a second plate connected to receive the pass control signal;
wherein during a read operation, the pass control signal causes a voltage of said node to increase before said transfer gate voltage causes the transfer gate transistor to transfer charge from the photodiode to said node.

2. The arrangement as claimed in claim 1 , wherein said pass transistor is a read transistor and during the read operation said pass control signal has a read voltage value.

3. The arrangement as claimed in claim 2 , wherein when said pass control signal has the read voltage value, a first read of a black signal value is made and then a second read of a photodiode signal value is made.

4. The arrangement as claimed in claim 3 , wherein said transfer gate voltage is at a first voltage level for the first and second reads and is at a second voltage level different from the first voltage level between the first and second reads.

5. The arrangement as claimed in claim 4 , wherein said first voltage level is lower than said second voltage level.

6. The arrangement as claimed in claim 1 , wherein said reset signal is pulsed at a beginning of said read operation.

7. The arrangement as claimed in claim 6 , wherein said pass control signal is pulsed after said reset signal is pulsed.

8. The arrangement as claimed in claim 7 , wherein transfer gate voltage is pulsed while said pass control signal is pulsed.

9. The arrangement as claimed in claim 1 , further comprising:
a storage capacitor coupled to said pass transistor; and
a read transistor coupled to said storage capacitor.

10. The arrangement as claimed in claim 1 , wherein the arrangement is implemented as an integrated circuit.

11. A circuit, comprising:
a photodiode;
a transfer transistor having a source-drain path coupled between the photodiode and a first intermediate node, said transfer transistor configured to be controlled by a transfer signal;
a reset transistor having a source-drain path coupled between a reset voltage node and the first intermediate node, said reset transistor configured to be controlled by a reset signal;
a first source follower transistor having a source-drain path coupled between a source follower voltage node and a second intermediate node, said first source follower transistor configured to be controlled by a voltage at said first intermediate node;
a pass transistor having a source-drain path coupled between the second intermediate node and a third intermediate node; and
a capacitor having a first plate connected to said first intermediate node and a second plate connected to a control terminal of the pass transistor and configured, during a read operation of said photodiode, to boost voltage at said first intermediate node before said transfer signal turns on said transfer transistor.

12. The circuit of claim 11 , wherein said capacitor is a boost capacitor.

13. The circuit of claim 11 , wherein said pass transistor is a read transistor configured to be controlled by a read signal.

14. The circuit of claim 11 , wherein said pass transistor is a selection transistor configured to be controlled by a selection signal.

15. The circuit of claim 14 , further comprising a storage capacitor coupled between the third intermediate node and a reference supply node.

16. The circuit of claim 15 , further comprising:
a second source follower transistor having a source-drain path coupled between the source follower voltage node and a fourth intermediate node, said second source follower transistor configured to be controlled by a voltage at said third intermediate node.

17. The circuit of claim 16 , further comprising:
a read transistor coupled between the fourth intermediate node and an output node.

18. The circuit of claim 15 , further comprising a bias transistor having a source-drain path coupled between the second intermediate node and the reference supply node, said bias transistor configured to be controlled by a bias signal.

19. A circuit, comprising:
a photodiode;
a transfer transistor having a source-drain path coupled between the photodiode and a first intermediate node, said transfer transistor configured to be controlled by a transfer signal;
a reset transistor having a source-drain path coupled between a reset voltage node and the first intermediate node, said reset transistor configured to be controlled by a reset signal;
a source follower transistor having a source-drain path coupled between a source follower voltage node and a second intermediate node, said source follower transistor configured to be controlled by a voltage at said first intermediate node;
a read transistor having a source-drain path coupled between the second intermediate node and a third intermediate node, said read transistor configured to be controlled by a read signal; and
a boost capacitor having a first plate connected to said first intermediate node and a second plate connected to a control terminal of the read transistor.

20. A circuit, comprising:
a photodiode;
a transfer transistor having a source-drain path coupled between the photodiode and a first intermediate node, said transfer transistor configured to be controlled by a transfer signal;
a reset transistor having a source-drain path coupled between a reset voltage node and the first intermediate node, said reset transistor configured to be controlled by a reset signal;
a first source follower transistor having a source-drain path coupled between a source follower voltage node and a second intermediate node, said first source follower transistor configured to be controlled by a voltage at said first intermediate node;
a selection transistor having a source-drain path coupled between the second intermediate node and a third intermediate node, said selection transistor configured to be controlled by a selection signal; and
a boost capacitor having a first plate connected to said first intermediate node and a second plate connected to a control terminal of the selection transistor.

21. The circuit of claim 20 , further comprising:
a second source follower transistor having a source-drain path coupled between the source follower voltage node and a fourth intermediate node, said second source follower transistor configured to be controlled by a voltage at said third intermediate node; and
a read transistor having a source-drain path coupled between the fourth intermediate node and an output node, said read transistor configured to be controlled by a read signal.

22. The circuit of claim 21 , further comprising a storage capacitor coupled between said third intermediate node and a reference supply node.

23. The circuit of claim 20 , further comprising a bias transistor having a source-drain path coupled between the second intermediate node and a reference supply node, said bias transistor configured to be controlled by a bias signal.

Assignees

• Stmicroelectronics (Grenoble 2) Sas
• Stmicroelectronics (Research & Development) Ltd
• STMicoelectronics (Grenoble 2 ) SAS

Inventors

• Storm Graeme
• Mandier Christophe
• Stark Laurence

Classifications

• H04N25/771

  comprising storage means other than floating diffusion · CPC title

• H04N25/626

  Reduction of noise due to residual charges remaining after image readout, e.g. to remove ghost images or afterimages · CPC title

• H04N25/57

  Control of the dynamic range · CPC title

• H04N25/59

  by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance · CPC title

• H04N25/00

  Circuitry of solid-state image sensors [SSIS]; Control thereof · CPC title