System in package process flow

Patent metadata

Field	Value
Publication number	US-9881898-B2
Application number	US-201213602650-A
Country	US
Kind code	B2
Filing date	Sep 4, 2012
Priority date	Nov 7, 2011
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate.

First claim

What is claimed is:

1. A method comprising:
(a) connecting a plurality of integrated circuit (IC) dies to a package substrate with the plurality of IC dies on a first side of the package substrate, leaving at least first, second, third, and fourth edge portions of the package substrate having exposed contacts adjacent to four respective sides of one of the plurality of IC dies, the first and second edge portions of the package substrate meeting at a first corner of the package substrate adjacent to a first corner of that one of the plurality of IC dies, the respective third and fourth edge portions of the package substrate meeting at a second corner of the package substrate adjacent to a second corner of that one of the IC dies;
(b) placing at least a first upper die package having a first edge portion and a second edge portion on the first side of the package substrate and over that one of the plurality of the IC dies, so as to cover and extend beyond the first corner of that one of the plurality of the IC dies in two perpendicular directions;
(c) connecting pads on the first and second edge portions of the first upper die package to the contacts of the first and second edge portions of the package substrate;
(d) placing a second upper die package having a third edge portion and a fourth edge portion over that one of the plurality of the IC dies that is partially overlaid by the first supper die package, so as to cover and extend beyond the second corner of that one of the plurality of the IC dies in two perpendicular directions, the second upper die package located diagonally from the first upper die package, the first and second upper die packages spaced apart so that neither of the first and second upper die packages lies over the other of the first and second upper die packages; and
(e) connecting pads on the third and fourth edge portions of the second upper die package to the contacts of the third and fourth edge portions of the package substrate.

2. The method of claim 1 , further comprising:
placing a third upper die package over the one of the plurality of IC dies, so that fifth and sixth edge portions of the third upper die package extend beyond the second and third edges of that one of the plurality of the IC dies,
placing a fourth upper die package over that one of the plurality of the IC dies, so that the seventh and eighth edge portions of the fourth upper die package extend beyond the first and fourth edges of that one of the plurality of the IC dies,
connecting pads on the fifth and sixth edge portions of the third upper die package to the contacts of the second and third edge portions of the package substrate; and
connecting pads on the seventh and eighth edge portions of the fourth upper die package to the contacts of the first and fourth edge portions of the package substrate.

3. The method of claim 1 , wherein
the first upper die package has solder on the pads of the first and second edge portions thereof, the method further comprising:
depositing a solder paste on the contacts of the first and second edge portions of the package substrate before step (c).

4. The method of claim 1 , further comprising:
placing solder on the contacts of the first and second edge portions of the package substrate; and
depositing a solder paste on the solder before step (c).

5. The method of claim 4 , wherein the solder is placed on the contacts of the first and second edge portions of the package substrate after step (a).

6. The method of claim 1 , further comprising placing solder on the contacts of the first and second edge portions of the package substrate before step (a).

7. The method of claim 4 , further comprising
applying a molded underfill material around the solder and above the first upper die package.

8. The method of claim 7 , wherein an underfill material is deposited between the one of the IC dies and the package substrate, between steps (a) and (b).

9. The method of claim 7 , further comprising depositing a first underfill material between the one of the IC dies and the package substrate, before applying the molded underfill material around the solder.

10. The method of claim 1 , further comprising:
placing a thermal interface material over the one of the IC dies before step (b).

11. A method comprising:
(a) connecting at least one integrated circuit (IC) die to a package substrate, so that first and second edge portions of the package substrate having contacts thereon extend beyond four edges of the at least one IC die;
(b) placing a first upper die package over the at least one IC die, with the at least one IC die located between the first upper die package and the package substrate, so as to cover and extend beyond a first corner of one of a plurality of the IC dies in two perpendicular directions,
(c) placing a second upper die package over that IC die, so as to cover and extend beyond a second corner of that one of the plurality of the IC dies in two perpendicular directions, the first and second upper die packages positioned diagonally from each other in a plane and spaced apart so that neither of the first and second upper die packages lies over the other of the first and second upper die packages;
(d) connecting pads on first and second edge portions of the first upper die package directly to the contacts of the first and second edge portions of the package substrate; and
(e) connecting pads on third and fourth edge portions of the second upper die package to the contacts of the third and fourth edge portions of the package substrate.

12. The method of claim 11 , wherein step (a) includes connecting the IC die of that one of the plurality of the IC dies to the package substrate using solder, the method further comprising applying a first underfill material around the solder, between steps (a) and (b).

13. The method of claim 12 , wherein the step of applying a first underfill material includes depositing the first underfill material between the that one of the plurality of the IC dies and the package substrate.

14. The method of claim 11 , further comprising placing a thermal interface material over the that one of the plurality of the IC dies before step (b).

15. A method comprising:
(a) flip chip mounting a plurality of integrated circuit (IC) dies over a package substrate, so that first and second edge portions of the package substrate having contacts thereon extend beyond two adjacent edges of one of the plurality of IC dies;
(b) placing at least a first upper die package over the one of the plurality of IC dies, so that the first upper die package is on a same side of the package substrate as the plurality of IC dies, so as to cover and extend beyond a first corner of the one of the plurality of IC dies in two perpendicular directions,
(c) connecting pads on first and second edge portions of the first upper die package to the contacts of the first and second edge portions of the package substrate;
(d) placing a second upper die package over the one of the plurality of IC dies that is partially overlaid by the first supper die package, so as to cover and extend beyond a second corner of the one of the plurality of IC dies in two perpendicular directions, so that the second upper die package is on the same side of the package substrate as the plurality of IC dies, the first and second upper die packages positioned diagonally from each other and spaced apart so that neither of the first and second upper die packages lies over the other of the first and second upper die packages; and
(e) connecting pads on third and fourth edge portions of the second upper die packag

Assignees

• Wang Tsung-Ding
• Lee Chien-Hsun
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Tsung-Ding
• Lee Chien-Hsun

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title