Method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9881836-B2
Application number	US-201113310311-A
Country	US
Kind code	B2
Filing date	Dec 2, 2011
Priority date	Sep 13, 2011
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

A method for manufacturing semiconductor devices comprises: applying a dual pulse power to the semiconductor device during metal electroplating a part of the semiconductor device and applying ultrasonic energy to said semiconductor device during the metal electroplating.

First claim

What is claimed is:

1. A method for manufacturing semiconductor devices, comprising:
applying a dual pulse power to the semiconductor device during metal electroplating on a part of the semiconductor device, and applying an ultrasonic wave to the semiconductor device during the metal electroplating;
wherein the dual pulse power has a pulse frequency ranging from 1800 kHz to 5000 kHz;
wherein the dual pulse power has a ratio of forward-pulse current to inverse-pulse current ranging from 5:1 to 10:1 during one pulse cycle;
wherein the dual pulse power has a ratio of forward-pulse duration to inverse-pulse duration ranging from 10:1 to 20:1 during one pulse cycle; and
wherein said ultrasonic wave has a frequency of 1000 Hz to 5000 Hz and a power of 50 W to 1500 W.

2. The method of claim 1 , wherein the part to be electroplated is an opening in a dielectric layer or in a substrate.

3. The method of claim 1 , wherein the ultrasonic wave is applied intermittently.

4. The method of claim 3 , wherein the applying of the ultrasonic wave is conducted periodically.

5. The method of claim 3 , wherein a duration of applying the ultrasonic wave each time is 5 seconds to 20 seconds.

6. The method of claim 1 , further comprising:
forming, before the electroplating, a metal seed layer on a surface of the part to be electroplated.

7. The method of claim 2 , wherein the opening comprises a trench or a hole.

8. The method of claim 7 , wherein the hole comprises a through hole or a blind via.

Assignees

• Zhou Ming
• Semiconductor Mfg International (Beijing) Corporation

Inventors

• Zhou Ming

Classifications

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/023 Primary

  the interconnections being through-semiconductor vias · CPC title

• H01L21/2885

  Electricity · mapped topic

• H01L21/76898 Primary

  Electricity · mapped topic