Dynamically addressable master-slave system and method for dynamically addressing slave units

Patent metadata

Field	Value
Publication number	US-9880950-B2
Application number	US-201514840151-A
Country	US
Kind code	B2
Filing date	Aug 31, 2015
Priority date	Oct 10, 2014
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

A master-slave system includes a master unit having a digital output for providing a signal or a serial signal sequence of signals, and at least two slave units. Each of the slave units includes at least one digital serial memory having a size of one bit, and each slave unit includes an input and an output. The slave units are serially connected to one another via the inputs and the outputs via a signal line ( 5 ). The output of a first slave unit is connected via the signal line to the digital output of the master unit. The master slave system is configured so that a signal supplied by the digital output is detected at the input of the slave unit, in order to raise the address of the corresponding slave unit in each case by the value “1”, to store the signal change in the memory and to output a signal corresponding to the content of the memory at the output of the memory.

First claim

The invention claimed is:

1. A master-slave system comprising:
a master unit having a digital output for supplying a serial signal sequence of signals, and
at least two slave units, wherein
each of the slave units includes at least one digital serial memory having a size of one bit, and each slave unit includes an input and an output,
the slave units are serially connected to one another via the inputs and the outputs via a signal line,
the input of a first slave unit is connected via the signal line to the digital output of the master unit,
the master slave system is configured so that a signal change of the serial sequence of signals supplied by the digital output is detected at the input of a first slave unit;
in reaction to the signal change, the master slave system is configured to raise the address of the corresponding slave unit in each case by the value “1”, to store the signal change in the memory, wherein only a positive change of flank is stored, and to output a signal corresponding to the content of the memory at the output of the respective slave-unit and thus at the input of the next slave-unit.

2. The master-slave system according to claim 1 , wherein n slave units are provided, wherein the output of n−1 slave units is connected to the input of the respective next adjacent slave unit in the series.

3. The master-slave system according to claim 1 , wherein the output of the last slave unit in the serial arrangement is connected to a digital input of the master unit via a return line.

4. The master-slave system according to claim 1 , wherein the master unit is designed as a memory-programmable control, a computer having corresponding hardware interfaces or not freely programmable control or as a unit having a push button for generating the signal.

5. The master-slave system according to claim 1 , wherein the master-slave system may switch from a lock mode to an address mode and vice versa, in which the addressing of the slave units is either locked or enabled.

6. The master-slave system according to claim 5 , wherein the master unit is designed for generating an address mode signal, in order to set the master-slave system in the address mode, and the address mode signal may be supplied via the digital output or via an optionally provided bus.

7. The master-slave system according to claim 5 , wherein the master unit is designed for generating a lock mode signal, in order to reset the master-slave system in the lock mode when the addressing has ended, and the lock mode signal may be supplied via the digital output or via an optionally provided bus.

8. The master-slave system according to claim 1 , wherein the serial digital memories are designed as shift registers.

9. A method for dynamically addressing slave units of a master-slave system according to claim 1 , wherein at the start of addressing, all slave units have the same address, and the content of all digital serial memories is the value “zero”, the method comprising:
setting the master-slave system in an address mode by means of an address mode signal supplied by the master unit,
generating a number of serial signals, which corresponds to the number of slave units and transmitting the signals over the signal line by means of the master unit,
raising a slave address of the slave unit addressed by each signal, in each case by the value “1” in reaction to when a signal change of the serial sequence of signals corresponding to the change of state is detected at the input to the slave unit, and setting the respective serial memory to the signaled state, wherein only a positive change of flank is stored, and forwarding a corresponding signal at the output of the corresponding slave unit and, therefore, to the input of the respective nearest adjacent slave unit,
returning from a signaled to a non-signaled state after each signal of the serial signal sequence of signals.

10. The method according to claim 9 , wherein the signaled state of the slave unit is forwarded to the next slave unit in the series, in each case delayed by one period as a result of its serial sequencing.

11. The method according to claim 9 , wherein a maximum time span is defined for the entire process, which in each case may elapse between two signal changes, wherein a termination of the address assignment and the resetting of the memory values and address values to the output value occurs as soon as the time span during a signal change is exceeded.

12. The method according to claim 9 , wherein the master unit generates one additional signal change beyond the number of slave units, such that the last slave unit in the series, after being addressed, is raised at its output by one additional address unit as a result of the additional signal change, via a return line at the input of the master unit, wherein the master unit detects the conclusion of the addressing process.

Assignees

• Ebm Papst Mulfingen Gmbh & Co Kg

Inventors

• Sauer Thomas
• Lipp Helmut
• Teuke Klaus
• Humm Markus
• Fessel Andreas
• Buerkert Martin

Classifications

• H04L61/2038

  Electricity · mapped topic

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/16 Primary

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• H04L12/40169

  Flexible bus arrangements (arrangements for maintenance or administration involving management of faults; events, alarms H04L41/06; automatic restoration of network faults H04L41/0654) · CPC title

• H04L61/5038

  for local use, e.g. in LAN or USB networks, or in a controller area network [CAN] · CPC title