Pulse-latch based bus design for increased bandwidth
US-2015363352-A1 · Dec 17, 2015 · US
Interface module for HW block
US9201818B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9201818-B2 |
| Application number | US-201214116604-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 10, 2012 |
| Priority date | May 11, 2011 |
| Publication date | Dec 1, 2015 |
| Grant date | Dec 1, 2015 |
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Abstract
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An interface module for a logic circuit block comprising a processing module, the interface module comprising a control interface for communicating one or more control messages; a data interface for accessing a data storage device; an interface logic block; and a core interface to the processing module, the core interface being connected to the interface logic block for communicating signals between the interface logic block and the processing module. The interface logic block is adapted to receive one or more incoming control message via the control interface; process the one or more control messages including accessing a data storage device via the data interface, initiating processing by the processing module via the core interface, receiving one or more signals from the processing module via the core interface; and to output one or more outgoing control message via the control interface.
First claim
Opening claim text (preview).
The invention claimed is: 1. An interface circuit for a logic circuit block, the logic circuit block comprising a processing circuit implemented as a hardware block core, the interface circuit comprising: a control interface configured to send and receive one or more control messages; a data interface configured to access a data storage device; an interface logic block connected to the control interface and to the data interface; a core interface connected to the processing…
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Physics · mapped topic
- G06F13/16Primary
Physics · mapped topic
Cross-Sectional Technologies · mapped topic
Cross-Sectional Technologies · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9201818B2 cover?
- An interface module for a logic circuit block comprising a processing module, the interface module comprising a control interface for communicating one or more control messages; a data interface for accessing a data storage device; an interface logic block; and a core interface to the processing module, the core interface being connected to the interface logic block for communicating signals be…
- Who is the assignee on this patent?
- Malmberg Magnus, Breschel Michael, Brkic Toni, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification G06F13/16. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).