Method for scrubbing and correcting DRAM memory data with internal error-correcting code (ECC) bits contemporaneously during self-refresh state

Patent metadata

Field	Value
Publication number	US-9880900-B2
Application number	US-201514963023-A
Country	US
Kind code	B2
Filing date	Dec 8, 2015
Priority date	Dec 8, 2015
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

In one embodiment, a method for updating a DRAM memory array is disclosed. The method comprises: a) transitioning the DRAM memory array from an idle state to a self-refresh state after a period of inactivity; b) initiating a refresh on the DRAM memory array using DRAM internal control circuitry; and c) during the refresh, performing an Error Correction Code (ECC) scrub operation of selected bits in an activated row of the DRAM memory array.

First claim

What is claimed is:

1. A method for updating a DRAM memory array, said method comprising:
a) transitioning the DRAM memory array from an idle state to a self-refresh state;
b) initiating a refresh on the DRAM memory array using DRAM internal control circuitry;
c) during the refresh, performing an Error Correction Code (ECC) scrub operation of selected bits in an activated row of the DRAM memory array; and
d) updating a refresh column counter.

2. The method of claim 1 , further comprising:
repeating the b) and c) for subsequent refresh operations to other rows in the DRAM memory array.

3. The method of claim 2 , wherein updating the refresh column counter comprises selecting a different set of bits from the selected bits from a sense amplifier buffer of the DRAM memory array for a subsequent ECC scrub operation.

4. The method of claim 3 , further comprising:
repeating the c) and d) to select and perform an ECC scrub of subsequent bits in the activated row.

5. The method of claim 3 , further comprising:
repeating the b), c) and d) for subsequent refresh operations to perform an ECC scrub over all columns for all rows of the DRAM memory array.

6. The method of claim 3 , wherein the ECC scrub operation comprises performing a virtual read and write operation to re-circulate selected data bits through an ECC repair module and store corrected data from the ECC repair module back in the sense amplifier buffer.

7. The method of claim 3 , further comprising:
performing an ECC scrub operation for remaining bits over a plurality of rows in the DRAM memory array during subsequent DRAM-initiated refresh cycles while in the self-refresh state.

8. The method of claim 5 , further comprising:
incrementing a bank counter to address a different portion of the DRAM memory array.

9. The method of claim 1 , wherein the ECC scrub operation comprises:
reading in the selected bits and corresponding ECC bits;
checking the selected bits to determine if they are correct using the corresponding ECC bits;
correcting the selected bits if the ECC bits indicate an error;
re-computing the ECC bits for the selected bits; and
writing corrected data and ECC bits back into a sense amplifier buffer of the DRAM memory array.

10. The method of claim 9 , wherein an address of any detected error is stored in a temporary buffer or register.

11. The method of claim 5 , wherein a time delay between internally generated refresh operations is adapted to accelerate scrubbing of multiple pages.

12. A method for updating a DRAM memory array, said method comprising:
a) transitioning the DRAM memory array from an idle state to a self-refresh state;
b) initiating a refresh on the DRAM memory array using DRAM internal control circuitry;
c) during the refresh, performing an Error Correction Code (ECC) scrub operation of selected bits in an activated row of the DRAM memory array, wherein the selected bits comprise multiple words; and
d) updating a refresh column counter.

13. The method of claim 12 , further comprising:
repeating the b) and c) for subsequent refresh operations to other rows in the DRAM memory array.

14. The method of claim 13 wherein updating the refresh column counter comprises selecting a different set of bits from the selected bits from a sense amplifier buffer of the DRAM memory array for a subsequent ECC scrub operation.

15. The method of claim 14 , further comprising:
repeating the c) and d) to select and perform an ECC scrub of subsequent bits in the activated row.

16. The method of claim 14 , wherein the ECC scrub operation comprises performing a virtual read and write operation to re-circulate selected data bits through an ECC repair module and store corrected data from the ECC repair module back in the sense amplifier buffer.

17. The method of claim 14 , further comprising:
performing an ECC scrub operation for remaining bits over a plurality of rows in the DRAM memory array during subsequent DRAM-initiated refresh cycles while in the self-refresh state.

18. The method of claim 12 , wherein the ECC scrub operation comprises:
reading in the selected bits and corresponding ECC bits;
checking the selected bits to determine if they are correct using the corresponding ECC bits;
correcting the selected bits if the ECC bits indicate an error;
re-computing the ECC bits for the selected bits; and
writing corrected data and ECC bits back into a sense amplifier buffer of the DRAM memory array.

19. The method of claim 18 , wherein an address of any detected error is stored in a temporary buffer or register.

20. An apparatus for updating a DRAM memory, the apparatus comprising:
a DRAM memory array, wherein the DRAM memory array is configured to:
a) transition the DRAM memory array to a self-refresh state from an idle state;
b) initiate a refresh on the DRAM memory array using DRAM internal control circuitry; and
c) during the refresh, performing an Error Correction Code (ECC) scrub operation of selected bits in an activated row of the DRAM memory array; and
d) updating a refresh column counter to select a different set of bits from a sense amplifier buffer of the DRAM memory array for a subsequent ECC scrub operation.

Assignees

• Nvidia Corp

Inventors

• Reed David
• Gupta Alok

Classifications

• G11C29/04 Primary

  Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals} · CPC title

• G11C2029/0409

  Online test · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C11/4082

  Address Buffers; level conversion circuits · CPC title

• G11C2211/4062

  Parity or ECC in refresh operations · CPC title