Memory system and method using partial ECC to achieve low power refresh and fast access to data

Patent metadata

Field	Value
Publication number	US-9286161-B2
Application number	US-201414464865-A
Country	US
Kind code	B2
Filing date	Aug 21, 2014
Priority date	Oct 11, 2006
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first set can be refreshed at a relatively slow rate to reduce the power consumed by the DRAM device. Error checking and correcting circuitry in the DRAM device corrects any data retention errors in the first set of memory cells caused by the relatively slow refresh rate. The memory cells in the second set are refreshed at a normal rate, which is fast enough that data retention errors do not occur. A mode register in the DRAM device may be programmed to select the size of the second set of memory cells.

First claim

I claim:

1. A method comprising:
while in a first mode:
refreshing a first set of memory cells of an array of a semiconductor device at a first rate, wherein a first type of data is stored in the first set of memory cells;
refreshing a second set of memory cells of the array at a second rate that is greater than the first rate, wherein a second type of data is stored in the second set of memory cells; and
correcting errors in the first type of data stored at the first set of the memory cells; and

while in a second mode:
refreshing the first set of memory cells and the second set of memory cells at the second rate.

2. The method of claim 1 , further comprising, responsive to entering the first mode, partitioning the memory cells of the array into the first set of memory cells and the second set of memory cells.

3. The method of claim 2 , further comprising:
storing a first type of data at the first set of memory cells; and
storing a second type of data at the second set of memory cells.

4. The method of claim 1 , further comprising, responsive to entering the first mode, generating syndrome data based on the first type of data stored at the first set of memory cells.

5. The method of claim 4 , wherein correcting errors in the first type of data stored at the first set of memory cells is based, at least in part, on the syndrome data.

6. The method of claim 5 , wherein correcting errors in the first type of data stored at the first set of memory cells based, at least in part, on the syndrome data comprises overwriting a portion of the first type of data stored at the first set of memory cells having errors with corrected data.

7. The method of claim 4 , further comprising, while in the first mode, storing the syndrome data at a syndrome memory.

8. The method of claim 7 , wherein the syndrome memory is included in a static random-access memory device.

9. The method of claim 1 , wherein correcting errors in the first type of data stored at the first set of memory cells is responsive to exiting the first mode.

10. The method of claim 1 , wherein the semiconductor device is a dynamic random-access memory device.

Assignees

• Micron Technology Inc

Inventors

• Pawlowski J Thomas

Classifications

• G11C11/406

  Management or control of the refreshing or charge-regeneration cycles · CPC title

• G11C2211/4067

  Refresh in standby or low power modes · CPC title

• G11C11/40622

  Partial refresh of memory arrays · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G06F11/1076 Primary

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title