Memory die temperature adjustment based on a power condition

Patent metadata

Field	Value
Publication number	US-9880752-B2
Application number	US-201615225884-A
Country	US
Kind code	B2
Filing date	Aug 2, 2016
Priority date	Sep 28, 2015
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

A device includes a memory device and a controller. The controller is coupled to the memory device. The controller is configured to, in response to receiving a request to perform a memory access at the memory device, determine that the memory device has a characteristic indicative of a temperature crossing. The controller is also configured to, in response to determining that the memory device has the characteristic indicative of the temperature crossing, determine that the memory device satisfies an availability criterion. The controller is further configured to, in response to determining that the memory device satisfies the availability criterion, increase a temperature of the memory device by performing memory operations on the memory device until detecting a condition related to the temperature.

First claim

What is claimed is:

1. A device comprising:
a memory device; and
a controller coupled to the memory device, the controller configured to:
in response to determining that a temperature of the memory device is less than a first threshold, determine that the memory device satisfies an availability criterion; and
in response to determining that the memory device satisfies the availability criterion, increase the temperature of the memory device by performing memory operations at the memory device until detecting a condition related to the temperature of the memory device.

2. The device of claim 1 , wherein performing the memory operations includes concurrently performing multiple memory operations, and wherein a number of memory operations concurrently performed is determined based on the availability criterion.

3. The device of claim 1 , wherein performing the memory operations includes sending an instruction to the memory device to initiate a sequence of memory operations.

4. The device of claim 3 , wherein the memory device includes read/write circuitry and a plurality of memory dies, and wherein the read/write circuitry is configured to perform a plurality of read operations at a first die of the plurality of memory dies in response to receiving the instruction.

5. The device of claim 1 , wherein the memory device includes read/write circuitry and a plurality of memory dies, wherein performing the memory operations includes sending a plurality of read instructions to the memory device, and wherein the read/write circuitry is configured to perform a read operation at a first die of the plurality of memory dies in response to receiving each read instruction of the plurality of read instructions.

6. The device of claim 1 , wherein the memory device includes a plurality of memory dies, wherein the controller is further configured to:
receive a request to write data to a first storage element of a plurality of storage elements of a first die of the plurality of memory dies, the first storage element corresponding to a multi-level cell (MLC);
in response to determining that the temperature of the memory device is less than the first threshold, write the data to a single-level cell (SLC) of the memory device; and
in response to detecting the condition related to the temperature, copy the data from the SLC to the MLC.

7. The device of claim 1 , wherein the controller is configured to determine that the memory device satisfies the availability criterion in response to determining that an activity level of the memory device is less than an activity threshold.

8. The device of claim 1 , wherein the controller is configured to determine that the memory device satisfies the availability criterion in response to determining that a power demand of the memory device is less than a power threshold.

9. The device of claim 1 , wherein the controller is configured to determine that the memory device satisfies the availability criterion in response to determining that a number of inactive dies is greater than an active die threshold.

10. The device of claim 1 , wherein detecting the condition related to the temperature of the memory device includes detecting that a temperature of a first die exceeds a second threshold.

11. The device of claim 10 , wherein the memory device includes a plurality of memory dies, and wherein the first die of the plurality of memory dies includes a temperature sensor.

12. The device of claim 1 , wherein the memory device includes a first die and a plurality of secondary dies that are proximate to the first die, the temperature corresponding to the first die, wherein the controller is further configured to identify a second die of the plurality of secondary dies, wherein the memory operations are performed on the second die to increase the temperature of the first die.

13. A device comprising:
a memory device; and
a controller configured to perform memory operations on the memory device to heat the memory device to at least a threshold temperature when power demand of the memory device is less than a power threshold.

14. The device of claim 13 , wherein heating the memory device includes performing a set of memory operations at the memory device, wherein a number of operations of the set of memory operations is determined based on the power threshold.

15. The device of claim 13 , wherein the memory device include a plurality of memory dies, wherein the power demand is associated with a number of active dies of the plurality of memory dies, and wherein heating the memory device includes performing a set of memory operations at one or more idle memory dies of the plurality of memory dies.

16. The device of claim 13 , wherein the power threshold is set such that a host request, received at the controller at a first time, can be satisfied when the power demand at the first time is less than or equal to the power threshold.

17. A method comprising:
in a device including a controller and a memory device, performing:
in response to determining that a temperature of the memory device is less than a threshold, determining that the memory device satisfies an availability criterion; and
in response to determining that the memory device satisfies the availability criterion, increasing the temperature of the memory device by performing memory operations at the memory device until detecting a condition related to the temperature.

18. The method of claim 17 , wherein performing the memory operations includes sending an instruction to the memory device to initiate a set of memory operations.

19. The method of claim 18 , further comprising determining, based on the availability criterion, a number of memory operations of the set of memory operations.

20. The method of claim 19 , wherein the number of memory operations of the set of memory operations is determined such that a request to access the memory device that is received from a host device during performance of the memory operations can be satisfied.

Assignees

• Western Digital Tech Inc

Inventors

• Reusswig Philip David
• Yang Nian Niles
• Shah Grishma
• Raghu Deepak
• Yadav Preeti
• Rao Prasanna Desai Sudhir
• Aggarwal Smita
• Lee Dana

Classifications

• G11C7/04 Primary

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G06F3/0634

  by changing the state or mode of one or more devices · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title