Thermal management for solid-state drive

US9880594B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9880594-B2
Application numberUS-201514810391-A
CountryUS
Kind codeB2
Filing dateJul 27, 2015
Priority dateApr 12, 2013
Publication dateJan 30, 2018
Grant dateJan 30, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A device structure includes a printed circuit board (PCB) comprising a thermal conduction plane, at least one heat generating component thermally connected to the thermal conduction plane, and a first frame portion thermally connected to the thermal conduction plane and at least partially enclosing the at least one heat generating component. The thermal conduction plane thermally connects the at least one heat generating component to the first frame portion by way of a plurality of vias from a surface of the PCB to the thermal conduction plane.

First claim

Opening claim text (preview).

What is claimed is: 1. A device structure for dissipating heat, comprising: a printed circuit board (PCB) comprising a thermal conduction plane; at least one heat generating component thermally connected to the thermal conduction plane by way of a first plurality of vias from a surface of the PCB to the thermal conduction plane; and a first frame portion mounted to the PCB and at least partially enclosing the at least one heat generating component; a first thermally-conductive layer disposed between an inner surface of the first frame portion and a side of the at least one heat generating component to thermally connect the at least one heat generating component to the first frame portion; and a second thermally-conductive layer disposed between the first frame portion and the surface of the PCB thermally connecting the first frame portion to the thermal conduction plane by way of a second plurality of vias from the surface of the PCB to the thermal conduction plane. 2. The device structure of claim 1 , further comprising: an array of solder balls disposed between the at least one heat generating component and the surface of the PCB, each solder ball being thermally connected to a respective one of the first plurality of vias to thermally connect the at least one heat generating component to the thermal conduction plane. 3. The device structure of claim 1 , further comprising: two or more heat generating components, wherein the first plurality of vias comprises two or more second groups of vias that thermally connect the thermal conduction plane to the two or more heat generating components. 4. The device structure of claim 1 , wherein the inner surface is a recessed surface of the first frame portion defined between first and second PCB mounting surfaces, the first frame portion being mounted to the PCB by way of the first and second PCB mounting surfaces. 5. The device structure of claim 1 , further comprising: a second frame portion, wherein the second plurality of vias comprises a second group of vias that thermally connect the thermal conduction plane to the second frame portion. 6. The device structure of claim 5 , wherein the first frame portion and the second frame portion are connected to the PCB on opposing sides of the PCB. 7. The device structure of claim 1 , wherein the thermal conduction plane is embedded within the PCB. 8. The device structure of claim 1 , wherein the thermal conduction plane is an electrical conductor. 9. A data storage device, comprising: a printed circuit board (PCB) comprising a thermal conduction plane and a plurality of vias from a surface of the PCB to the thermal conduction plane; at least one frame thermally connected to the PCB by way of one or more mounting portions of the at least one frame; one or more electronic components connected to the PCB, wherein the one or more electronic components are thermally connected to the thermal conduction plane thermally by way of the plurality of vias; at least one first thermally-conductive layer disposed between the mounting portions of the at least one frame and the PCB; and at least one second thermally-conductive layer disposed between the one or more electronic components and an inner surface of the at least one frame, wherein the first and second thermally-conductive layers facilitate separate paths of heat dissipation from the one or more electronic components. 10. The data storage device of claim 9 , wherein at least some of the plurality of vias connect the thermal conduction plane to the at least one first thermally-conductive layer to facilitate thermally connecting the one or more electronic components to the at least one frame. 11. The data storage device of claim 9 , further comprising: an array of solder balls disposed between the PCB and at least one of the one or more electronic components, wherein each solder ball is thermally connected to a respective one of the plurality of vias. 12. The data storage device of claim 9 , wherein two frames are thermally connected to the PCB, with one of the two flames and a side of the PCB at least partially encasing the one or more electronic components. 13. The data storage device of claim 9 , wherein the thermal conduction plane is embedded within the PCB. 14. The data storage device of claim 9 , wherein the PCB comprises multiple thermal conduction planes, each plane comprising a material of a different thermal conductivity. 15. The data storage device of claim 9 , wherein the one or more electronic components are memory devices. 16. The data storage device of claim 9 , wherein at least one of the at least one frames mounted to the PCB comprises an exterior surface having a plurality of protrusions that extend a surface area of the exterior surface. 17. The data storage device of claim 16 , wherein each of the plurality of protrusions are rectangular or cylindrical.

Assignees

Inventors

Classifications

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • Bump connectors and die-attach connectors · CPC title

  • for flat cards, e.g. credit cards · CPC title

  • Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence) · CPC title

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Frequently asked questions

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What does patent US9880594B2 cover?
A device structure includes a printed circuit board (PCB) comprising a thermal conduction plane, at least one heat generating component thermally connected to the thermal conduction plane, and a first frame portion thermally connected to the thermal conduction plane and at least partially enclosing the at least one heat generating component. The thermal conduction plane thermally connects the a…
Who is the assignee on this patent?
Western Digital Tech Inc
What technology area does this patent fall under?
Primary CPC classification H10W40/25. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 30 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).