Updating of a recipe for evaluating a manufacturing stage of an electrical circuit

Patent metadata

Field	Value
Publication number	US-9880550-B2
Application number	US-201514667086-A
Country	US
Kind code	B2
Filing date	Mar 24, 2015
Priority date	Mar 24, 2015
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

A computerized system that may include a recipe module and a yield diagnostics module. The yield diagnostics module may be configured to generate evaluation results that are indicative of an outcome of an evaluation process of at least one manufacturing stage of at least one electrical circuit. The evaluation results differ from end of line (EOL) results. The recipe module may be configured to receive EOL results relating to the at least one electrical circuit, to receive the evaluation results relating to the at least one electrical circuit; to correlate the evaluation results and the EOL results to provide correlation results; and respond to the correlation results. The responding to the correlation results may include determining whether to alter a recipe in response to the correlation results and altering the recipe if it is determined to alter the recipe.

First claim

What is claimed is:

1. A method for evaluating a recipe used to evaluate a plurality of electrical circuits that include microscopic structural elements, the method executed by a computerized system and comprising:
generating or receiving, at a computer system, evaluation results that are indicative of an outcome of an evaluation process of at least one manufacturing stage of at least one electrical circuit in the plurality of electrical circuits, wherein the evaluation results differ from end of line (EOL) results and include a plurality of results generated from evaluation processes that differ from each other by one or more setup parameters;
receiving or generating, at the computer system, EOL results relating to the at least one electrical circuit and that indicate the existence of one or more physical defects of the at least one electrical circuit;
correlating, at the computer system, the evaluation results and the EOL results to provide correlation results; and
determining, at the computer system, whether to alter the recipe in response to the correlation results and, if it is determined to alter the recipe, altering the recipe and using the altered recipe in future processes for evaluating a plurality of electrical circuits that include microscopic elements.

2. The method according to claim 1 wherein the correlating comprises categorizing defects to one of the following categories: detected fault-causing defect, non-fault-causing defects and undetected fault-causing defects.

3. The method according to claim 2 comprising altering the recipe in response to the categorizing of defects.

4. The method according to claim 2 comprising altering the recipe to include an evaluation of locations that correspond to locations of undetected fault causing defects.

5. The method according to claim 2 comprising altering the recipe to include an evaluation of locations that correspond to locations of detected fault causing defect.

6. The method according to claim 2 comprising adding to the recipe of a scanning electron microscopy review of locations that correspond to locations of at least one category of defect.

7. The method according to claim 1 comprising adding to the recipe a hot spot inspection.

8. The method according to claim 1 comprising retrieving design data about the electrical circuit and evaluating the correlation results in response to the design data.

9. A non-transitory computer readable medium that stores instructions that once executed by a computerized system cause the computerized system to execute the stages of:
generating or receiving evaluation results that are indicative of an outcome of an evaluation process of at least one manufacturing stage of at least one electrical circuit; wherein the evaluation results differ from end of line (EOL) results and include a plurality of results generated from evaluation processes that differ from each other by one or more setup parameters;
receiving or generating EOL results relating to the at least one electrical circuit and that indicate the existence of one or more physical defects of the at least one electrical circuit;
correlating the evaluation results and the EOL results to provide correlation results; and
determining, at the computer system, whether to alter the recipe in response to the correlation results and, if it is determined to alter the recipe altering the recipe and using the altered recipe in future processes for evaluating a plurality of electrical circuits.

10. The non-transitory computer readable medium according to claim 9 wherein the correlating comprises categorizing defects to one of the following categories:
detected fault-causing defect,
non-fault-causing defects, and
undetected fault-causing defects.

11. The non-transitory computer readable medium according to claim 10 that stores instructions for altering the recipe in response to the categorizing of defects.

12. The non-transitory computer readable medium according to claim 10 that stores instructions for altering the recipe to include an evaluation of locations that correspond to locations of undetected fault causing defects.

13. The non-transitory computer readable medium according to claim 10 that stores instructions for altering the recipe to include an evaluation of locations that correspond to locations of detected fault causing defect.

14. The non-transitory computer readable medium according to claim 10 that stores instructions for adding to the recipe of a scanning electron microscopy review of locations that correspond to locations of at least one category of defect.

15. A computerized system comprising:
a yield diagnostics module configured to generate, from an evaluation recipe, evaluation results that are indicative of an outcome of an evaluation process of at least one manufacturing stage of at least one electrical circuit in the plurality of electrical circuits, wherein the evaluation results differ from end of line (EOL) results and include a plurality of results generated from evaluation processes that differ from each other by one or more setup parameters; and
a recipe module configured to: (i) receive EOL results relating to the at least one electrical circuit and that indicate the existence of one or more physical defects of the at least one electrical circuit, (ii) receive the evaluation results relating to the at least one electrical circuit; (iii) correlate the evaluation results and the EOL results to provide correlation results; and (iv) determine whether to alter the recipe in response to the correlation results and, if it is determined to alter the recipe, altering the recipe and using the altered recipe in future processes for evaluating a plurality of electrical circuits that include microscopic elements.

Assignees

• Applied Materials Israel Ltd

Inventors

• Wachs Amir

Classifications

• G05B2219/31443

  Keep track of nc program, recipe program · CPC title

• Y02P90/14

  Cross-Sectional Technologies · mapped topic

• G05B2219/45031

  Manufacturing semiconductor wafers · CPC title

• Y02P90/20

  Cross-Sectional Technologies · mapped topic

• Y02P90/22

  Cross-Sectional Technologies · mapped topic