Extracting comprehensive design guidance for in-line process control tools and methods

Patent metadata

Field	Value
Publication number	US-9400865-B2
Application number	US-201514735596-A
Country	US
Kind code	B2
Filing date	Jun 10, 2015
Priority date	Jun 13, 2014
Publication date	Jul 26, 2016
Grant date	Jul 26, 2016

Abstract

Methods and systems for extracting comprehensive design guidance for in-line process control of wafers are provided. One method includes automatically identifying potential marginalities in a design for a device to be formed on a wafer. The method also includes automatically generating information for the potential marginalities. The automatically generated information is used to set up process control for the wafer.

First claim

What is claimed is:

1. A computer-implemented method for generating information for setting up process control for a wafer, comprising:
automatically identifying potential marginalities in a design for a device to be formed on a wafer; and
automatically generating information for the potential marginalities, wherein the automatically generated information is used to set up process control for the wafer, and wherein said automatically identifying and said automatically generating are performed by one or more computer systems.

2. The method of claim 1 , wherein the automatically generated information is not sufficient for use in fabrication of the device in its entirety.

3. The method of claim 1 , wherein the potential marginalities are automatically identified based on information provided by a designer of the device.

4. The method of claim 1 , wherein the potential marginalities are automatically identified based on information about electrical, logical, functional, and behavioral attributes of different areas within the device.

5. The method of claim 1 , wherein at least one of the potential marginalities is discovered through a simulation.

6. The method of claim 1 , wherein at least one of the potential marginalities is discovered through information about criticality of a design element for function or testing of the device.

7. The method of claim 1 , wherein at least one of the potential marginalities is discovered through prior knowledge of functional or performance deficiencies of a design element of the device.

8. The method of claim 1 , wherein at least one of the potential marginalities is identified based on electrical relevance of elements of the design to function of the device.

9. The method of claim 1 , wherein at least one of the potential marginalities is identified based on one or more elements of the design that are designed for testability of the device.

10. The method of claim 1 , wherein at least one of the potential marginalities is identified based on constraints on performance of a block in the design.

11. The method of claim 1 , wherein automatically generating the information comprises querying design elements corresponding to the potential marginalities against a physical design database for the device.

12. The method of claim 11 , wherein automatically generating the information further comprises generating a design data file containing physical design elements that result from said querying.

13. The method of claim 1 , wherein the automatically generated information for the potential marginalities comprises one or more physical attributes of physical design elements in the design corresponding to the potential marginalities.

14. The method of claim 1 , further comprising modifying one or more physical design elements in the design corresponding to the potential marginalities based on one or more parameters of the process control.

15. The method of claim 1 , wherein said automatically identifying and said automatically generating are performed by a fabless entity, and wherein the process control is set up based on the automatically generated information by a fab after receiving the information from the fabless entity.

16. The method of claim 1 , wherein the process control comprises an inspection process performed during fabrication of the device.

17. The method of claim 1 , wherein the process control comprises a defect review process performed during fabrication of the device.

18. The method of claim 1 , wherein the process control comprises a metrology process performed during fabrication of the device.

19. The method of claim 1 , wherein the process control comprises a failure analysis process performed after electrical testing of the device.

20. The method of claim 1 , wherein the one or more computer systems comprise an electronic design automation tool.

21. The method of claim 1 , wherein the design for the device used for said automatically identifying comprises design information that is available prior to design rule checking performed on the design.

22. The method of claim 1 , wherein at least some of the potential marginalities are automatically identified prior to design rule checking performed on the design.

23. The method of claim 1 , wherein at least some of the potential marginalities are automatically identified at different points in an electronic design automation process performed for the design, and wherein the automatically generated information comprises information for at least two of the potential marginalities that are automatically identified at the different points in the electronic design automation process.

24. The method of claim 1 , wherein the automatically generated information comprises information indicating different types of the potential marginalities.

25. The method of claim 24 , wherein the information indicating the different types of the potential marginalities is encrypted by an owner of the design.

26. The method of claim 24 , wherein the information indicating the different types of the potential marginalities is used to set up different types of the process control for the wafer.

27. A non-transitory computer-readable medium, storing program instructions executable on a computer system for performing a computer-implemented method for generating information for setting up process control for a wafer, wherein the computer-implemented method comprises:
automatically identifying potential marginalities in a design for a device to be formed on a wafer; and
automatically generating information for the potential marginalities, wherein the automatically generated information is used to set up process control for the wafer.

28. A system configured to generate information for setting up process control for a wafer, comprising:
a process control tool configured to determine information for one or more characteristics of a physical version of a wafer on which at least a portion of a device has been formed; and
one or more computer subsystems configure for:
automatically identifying potential marginalities in a design for the device; and
automatically generating information for the potential marginalities, wherein the automatically generated information is used to set up process control for the wafer performed by the process control tool.

29. The system of claim 28 , wherein the automatically generated information is not sufficient for use in fabrication of the device in its entirety.

30. The system of claim 28 , wherein the potential marginalities are automatically identified based on information provided by a designer of the device.

31. The system of claim 28 , wherein the potential marginalities are automatically identified based on information about electrical, logical, functional, and behavioral attributes of different areas within the device.

32. The system of claim 28 , wherein at least one of the potential marginalities is discovered through a simulation.

33. The system of claim 28 , wherein at least one of the potential marginalities is discovered through information about criticality of a design element for function or testing of the device.

34. The system of claim 28 , wherein at least one of the potential marginalities is discovered through prior knowledge of func

Assignees

• Kla Tencor Corp
• Kla Tencor Corp

Inventors

• Kekare Sagar A
• Bakarian Sergei G

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/23 Primary

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• G06F30/20 Primary

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F17/5009

  Physics · mapped topic