Transistors having strained channel under gate in a recess

Patent metadata

Field	Value
Publication number	US-9876109-B2
Application number	US-201715465936-A
Country	US
Kind code	B2
Filing date	Mar 22, 2017
Priority date	Apr 4, 2014
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

Some embodiments include a construction having a second semiconductor material over a first semiconductor material. A region of the second semiconductor material proximate the first semiconductor material has strain due to different lattice characteristics of the first and second semiconductor materials. A transistor gate extends downwardly into the second semiconductor material. Gate dielectric material is along sidewalls and a bottom of the transistor gate. Source/drain regions are along the sidewalls of the transistor gate, and the gate dielectric material is between the source/drain regions and the transistor gate. A channel region extends between the source/drain regions and is under the bottom of the transistor gate. At least some of the channel region is within the strained region.

First claim

We claim:

1. A semiconductor construction, comprising:
a first semiconductor material;
a second semiconductor material over the first semiconductor material and having a strained region proximate the first semiconductor material;
a transistor gate extending downwardly into the second semiconductor material;
conductively-doped source/drain regions proximate sidewalls of the transistor gate and extending downwardly into the second semiconductor material;
a channel region extending between the conductively-doped source/drain regions and under the bottom of the transistor gate, at least some of the channel region being within the strained region;
wherein upper surfaces of the conductively-doped source/drain regions are above an upper surface of the transistor gate; and
wherein the first semiconductor material comprises germanium and the second semiconductor material comprises silicon.

2. The semiconductor construction of claim 1 wherein the source/drain regions are less deep than the transistor gate within the second semiconductor material.

3. The semiconductor construction of claim 1 wherein the channel region is container-shaped; and wherein an interface where the first and second semiconductor materials join is configured to be container-shaped, with the container-shaped channel region being nested within the container-shaped interface.

4. A semiconductor construction, comprising:
a first semiconductor material;
a second semiconductor material over the first semiconductor material and having a strained region proximate the first semiconductor material;
a transistor gate extending downwardly into the second semiconductor material;
conductively-doped source/drain regions proximate sidewalls of the transistor gate and extending downwardly into the second semiconductor material;
a channel region extending between the conductively-doped source/drain regions and under the bottom of the transistor gate, at least some of the channel region being within the strained region;
wherein upper surfaces of the conductively-doped source/drain regions are above an upper surface of the transistor gate; and
wherein the first semiconductor material comprises a mixture of germanium and silicon, and wherein the second semiconductor material comprises silicon.

5. A semiconductor construction, comprising:
a first semiconductor material;
a second semiconductor material over the first semiconductor material and joining the first semiconductor material along an interface; a strained region of the second semiconductor material being proximate the interface;
a transistor gate extending into the second semiconductor material;
an intervening region of the second semiconductor material being between a bottom of the transistor gate and the first semiconductor material; an entirety of the intervening region being encompassed by the strained region;
dielectric material along sidewalls and the bottom of the transistor gate;
source/drain regions proximate the transistor gate, and spaced from the transistor gate by the dielectric material; the source/drain regions extending into the second semiconductor material to a depth less than a depth of the transistor gate within the second semiconductor material;
wherein a channel region extends between the source/drain regions and under the bottom of the transistor gate;
wherein the second semiconductor material comprises silicon; and
wherein the first semiconductor material comprises a mixture of germanium and silicon.

6. The semiconductor construction of claim 5 wherein the channel region is container-shaped; and wherein the interface is also container-shaped, with the container-shaped channel region being nested within the container-shaped interface.

7. The semiconductor construction of claim 5 wherein a thickness of the channel region is substantially consistent along an entirety of the channel region.

8. A semiconductor construction, comprising:
a first semiconductor material;
a second semiconductor material over the first semiconductor material and joining the first semiconductor material along an interface; a strained region of the second semiconductor material being proximate the interface;
a transistor gate extending into the second semiconductor material;
an intervening region of the second semiconductor material being between a bottom of the transistor gate and the first semiconductor material; an entirety of the intervening region being encompassed by the strained region;
dielectric material along sidewalls and the bottom of the transistor gate;
source/drain regions proximate the transistor gate, and spaced from the transistor gate by the dielectric material; the source/drain regions extending into the second semiconductor material to a depth less than a depth of the transistor gate within the second semiconductor material;
wherein a channel region extends between the source/drain regions and under the bottom of the transistor gate;
wherein the second semiconductor material comprises silicon; and
wherein the first semiconductor material comprises a mixture of germanium and carbon.

9. A semiconductor construction, comprising:
a first semiconductor material;
a second semiconductor material over the first semiconductor material and joining the first semiconductor material along an interface; a strained region of the second semiconductor material being proximate the interface;
a transistor gate extending into the second semiconductor material;
an intervening region of the second semiconductor material being between a bottom of the transistor gate and the first semiconductor material; an entirety of the intervening region being encompassed by the strained region;
dielectric material along sidewalls and the bottom of the transistor gate;
source/drain regions proximate the transistor gate, and spaced from the transistor gate by the dielectric material; the source/drain regions extending into the second semiconductor material to a depth less than a depth of the transistor gate within the second semiconductor material;
wherein a channel region extends between the source/drain regions and under the bottom of the transistor gate;
wherein the second semiconductor material comprises silicon; and
wherein the first semiconductor material comprises a II/VI mixture, a IV/VI mixture or a II/V mixture.

10. The semiconductor construction of claim 9 wherein a portion of the channel region is not within the strained region.

Assignees

• Micron Technology Inc

Inventors

• Mayuzumi Satoru
• Fischer Mark

Classifications

• H01L27/2481

  Electricity · mapped topic

• H01L29/1054

  Electricity · mapped topic

• H01L27/088

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic

• H01L27/10876

  Electricity · mapped topic