Transistor with hole barrier layer

Patent metadata

Field	Value
Publication number	US-9876082-B2
Application number	US-201514700712-A
Country	US
Kind code	B2
Filing date	Apr 30, 2015
Priority date	Apr 30, 2015
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

An apparatus includes a channel layer, a first layer, a hole barrier layer and a second layer. The channel layer may be configured to carry a drain current in response to a voltage at a gate node. The first layer may be between the channel layer and the gate node. The first layer generally has a first bandgap. The hole barrier layer may be in contact with the first layer. The hole barrier layer generally has a second bandgap that (i) forms a valence band offset relative to the first bandgap and (ii) is configured to impede holes generated in one or more of the channel layer and the first layer from reaching the gate node. The gate node may be in contact with the second layer. The apparatus generally forms a field effect transistor.

First claim

The invention claimed is:

1. An apparatus comprising:
a channel layer configured to carry a drain current in response to a voltage at a gate node;
a spacer layer in contact with said channel layer;
a doping layer in contact with said spacer layer;
a first layer in contact with said doping layer, wherein said first layer has a first bandgap;
a hole barrier layer in contact with said first layer, wherein said hole barrier layer has a second bandgap that (i) forms a valence band offset relative to said first bandgap, and (ii) is configured to impede holes generated in one or more of said channel layer and said first layer from reaching said gate node; and
a second layer in contact with said hole barrier layer, wherein (i) said second layer has said first bandgap, (ii) said gate node is in contact with said second layer and, (iii) said apparatus comprises a field effect transistor.

2. The apparatus according to claim 1 , wherein said hole barrier layer comprises a III-V semiconductor.

3. The apparatus according to claim 1 , wherein (i) said hole barrier layer comprises an In( 1-x) Ga x P semiconductor, and (ii) X ranges from approximately 0.3 to 0.7.

4. The apparatus according to claim 1 , wherein said first layer and said second layer each comprise an AlGaAs semiconductor.

5. The apparatus according to claim 1 , further comprising (i) an etch-stop layer in contact with said second layer, (ii) a cap layer in contact with said etch-stop layer, and (iii) a recess in both said cap layer and said etch-stop layer, wherein said gate node is disposed in said recess and on said second layer.

6. The apparatus according to claim 5 , wherein said etch stop layer resides (i) between said second layer and a source node, and (ii) between said second layer and a drain node.

7. The apparatus according to claim 5 , further comprising (i) an additional etch-stop layer in contact with said cap layer, (ii) an additional cap layer in contact with said additional etch-stop layer, and (iii) an additional recess in both said additional cap layer and said additional etch-stop layer overlapping said recess.

8. The apparatus according to claim 1 , further comprising another doping layer.

9. The apparatus according to claim 1 , wherein said field effect transistor comprises one of (i) a pseudomorphic high electron mobility transistor, and (ii) a metal-semiconductor transistor.

10. The apparatus according to claim 1 , wherein said field effect transistor has a single heterojunction.

11. A method for fabricating a transistor, comprising the steps of:
forming a channel layer configured to carry a drain current in response to a voltage at a gate node;
forming a spacer layer in contact with said channel layer;
forming a doping layer in contact with said spacer layer;
forming a first layer in contact with said doping layer, wherein said first layer has a first bandgap;
forming a hole barrier layer in contact with said first layer, wherein said hole barrier layer has a second bandgap that (i) forms a valence band offset relative to said first bandgap, and (ii) is configured to impede holes generated in one or more of said channel layer and said first layer from reaching said gate node;
forming a second layer in contact with said hole barrier layer, wherein said second layer has said first bandgap; and
forming said gate node in contact with said second layer, wherein said transistor comprises a field effect transistor.

12. The method according to claim 11 , wherein said hole barrier layer comprises a III-V semiconductor.

13. The method according to claim 11 , wherein (i) said hole barrier layer comprises an In( 1-x) Ga x P semiconductor, and (ii) X ranges from approximately 0.3 to 0.7.

14. The method according to claim 11 , wherein said first layer and said second layer each comprise an AlGaAs semiconductor.

15. The method according to claim 11 , further comprising the steps of:
forming an etch-stop layer in contact with said second layer;
forming a cap layer in contact with said etch-stop layer; and
forming an additional recess in both said cap layer and said etch-stop layer, wherein said gate node is disposed in said recess and on said second layer.

16. The method according to claim 15 , further comprising the steps of:
forming an additional etch-stop layer in contact with said cap layer;
forming an additional cap layer in contact with said additional etch-stop layer; and
forming an additional recess in both said additional cap layer and said additional etch stop layer overlapping said recess.

17. The method according to claim 15 , wherein said etch stop layer resides (i) between said second layer and a source node, and (ii) between said second layer and a drain node.

18. The method according to claim 11 , further comprising the step of:
forming another doping layer.

19. The method according to claim 11 , wherein said field effect transistor comprises one of (i) a pseudomorphic high electron mobility transistor, and (ii) a metal-semiconductor transistor.

20. A field effect transistor fabricated in accordance with the method of claim 11 .

Assignees

• Macom Tech Solutions Holdings Inc

Inventors

• Hanson Allen W
• Cueva Gabriel R
• Struble Wayne M
• Zhang Yan

Classifications

• H01L29/432

  Electricity · mapped topic

• H01L29/7785

  Electricity · mapped topic

• H01L29/7784

  Electricity · mapped topic

• H01L29/205 Primary

  Electricity · mapped topic

• H01L29/66462

  Electricity · mapped topic