Method for manufacturing TFT substrate

Patent metadata

Field	Value
Publication number	US-9876040-B1
Application number	US-201614912927-A
Country	US
Kind code	B1
Filing date	Jan 29, 2016
Priority date	Dec 3, 2015
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

The present invention provides a method for manufacturing a TFT substrate, in which after induced crystallization is conducted by implanting ions into an amorphous silicon layer, there is no need to completely remove the ion induction layer formed on the surface of a poly-silicon layer so obtained and instead, a half-tone mask based operation is applied to remove only a portion of the ion induction layer corresponding to a channel zone and there is no need for re-conducting ion implantation subsequently for source/drain contact zones, thereby saving the mask necessary for re-conducting ion implantation. Further, the source/drain electrodes are also formed with the half-tone mask based operation so as to save the mask necessary for making the source/drain electrodes. Further, the source/drain electrodes are formed first so that the formation of an interlayer insulation layer can be omitted thereby saving the mask necessary for forming the interlayer insulation layer. Through the adoption of a half-tone mask base operation, the method for manufacturing a TFT substrate according to the present invention can reduce the nine masks that are involved in the prior art techniques to only six masks, thereby effectively simplifying the manufacturing process, improving manufacturing efficiency, and saving manufacturing cost.

First claim

What is claimed is:

1. A method for manufacturing a thin-film transistor (TFT) substrate, comprising the following steps:
(1) providing a base plate, depositing a buffer layer on the base plate, and depositing an amorphous silicon layer on the buffer layer;
(2) subjecting the amorphous silicon layer to ion implantation and conducting high temperature baking to have the amorphous silicon crystallized and converted into poly-silicon to form a poly-silicon layer located on the buffer layer and an ion induction layer located on the poly-silicon layer;
(3) depositing a first metal layer on the ion induction layer, coating photoresist on the first metal layer, providing a half-tone mask and using the half-tone mask to subject the photoresist to exposure and development to form a first photoresist segment and a second photoresist segment that are spaced from each other, wherein the first photoresist segment has two side areas having a thickness that is greater than a thickness of a central area;
(4) using the first photoresist segment and the second photoresist segment as a shielding layer to subject the first metal layer, the ion induction layer, the poly-silicon layer to etching so as to form an island-like semiconductor and source/drain area;
(5) subjecting the first photoresist segment and the second photoresist segment to ashing to remove the central area of the first photoresist segment, using a remaining portion of the first photoresist segment as a shielding layer to subject the first metal layer and the ion induction layer contained in the island-like semiconductor and source/drain area to etching to obtain an island-like semiconductor layer having a channel zone, source/drain contact zones located on the island-like semiconductor layer, and source/drain electrodes located on the source/drain contact zones; and peeling off remaining portions of the first photoresist segment and the second photoresist segment;
(6) depositing a gate insulation layer on the source/drain electrodes; depositing a second metal layer on the gate insulation layer and subjecting the second metal layer to patterning to form a gate electrode;
(7) forming a protection layer on the gate insulation layer and the gate electrode; forming a planarization layer on the protection layer; forming a via in the planarization layer, the protection layer, and the gate insulation layer to correspond to the source/drain electrodes; and
(8) forming a cathode on the planarization layer such that the cathode is connected through the via to the source/drain electrodes; forming a pixel definition layer on the planarization layer and forming an opening in the pixel definition layer to expose a portion of the cathode; conducting vapor depositing of an organic light-emitting diode (OLED) in the opening.

2. The method for manufacturing a TFT substrate as claimed in claim 1 , wherein in step (1), the base plate comprises a glass plate.

3. The method for manufacturing a TFT substrate as claimed in claim 1 , wherein in step (1), the buffer layer comprises a silicon nitride layer, a silicon oxide layer, or a combination thereof; the buffer layer has a thickness of 2000-4000 Å.

4. The method for manufacturing a TFT substrate as claimed in claim 1 , wherein in step (1), the amorphous silicon layer has a thickness of 2000-4000 Å.

5. The method for manufacturing a TFT substrate as claimed in claim 1 , wherein in step (2), ions implanted into the amorphous silicon layer comprise boron ions or nickel ions.

6. The method for manufacturing a TFT substrate as claimed in claim 1 , wherein in step (3), the first metal layer comprises one of molybdenum, aluminum, and copper, or a stacked combination of multiple ones thereof; the first metal layer has a thickness of 2000-4000 Å.

7. The method for manufacturing a TFT substrate as claimed in claim 1 , wherein in step (6), the gate insulation layer comprises a silicon nitride layer, a silicon oxide layer, or a combination thereof; the gate insulation layer has a thickness of 2000-4000 Å.

8. The method for manufacturing a TFT substrate as claimed in claim 1 , wherein in step (6), the second metal layer comprises one of molybdenum, aluminum, and copper, or a stacked combination of multiple ones thereof; the second metal layer has a thickness of 2000-4000 Å.

9. The method for manufacturing a TFT substrate as claimed in claim 1 , wherein in step (7), the protection layer comprises a silicon nitride layer, a silicon oxide layer, or a combination thereof; the protection layer has a thickness of 2000-4000 Å.

10. The method for manufacturing a TFT substrate as claimed in claim 1 , wherein in step (8), the cathode comprises a composition structure of indium tin oxide/silver/indium tin oxide or a single layer of metallic silver; the cathode has a thickness of 1000-3000 Å.

11. A method for manufacturing a thin-film transistor (TFT) substrate, comprising the following steps:
(1) providing a base plate, depositing a buffer layer on the base plate, and depositing an amorphous silicon layer on the buffer layer;
(2) subjecting the amorphous silicon layer to ion implantation and conducting high temperature baking to have the amorphous silicon crystallized and converted into poly-silicon to form a poly-silicon layer located on the buffer layer and an ion induction layer located on the poly-silicon layer;
(3) depositing a first metal layer on the ion induction layer, coating photoresist on the first metal layer, providing a half-tone mask and using the half-tone mask to subject the photoresist to exposure and development to form a first photoresist segment and a second photoresist segment that are spaced from each other, wherein the first photoresist segment has two side areas having a thickness that is greater than a thickness of a central area;
(4) using the first photoresist segment and the second photoresist segment as a shielding layer to subject the first metal layer, the ion induction layer, the poly-silicon layer to etching so as to form an island-like semiconductor and source/drain area;
(5) subjecting the first photoresist segment and the second photoresist segment to ashing to remove the central area of the first photoresist segment, using a remaining portion of the first photoresist segment as a shielding layer to subject the first metal layer and the ion induction layer contained in the island-like semiconductor and source/drain area to etching to obtain an island-like semiconductor layer having a channel zone, source/drain contact zones located on the island-like semiconductor layer, and source/drain electrodes located on the source/drain contact zones; and peeling off remaining portions of the first photoresist segment and the second photoresist segment;
(6) depositing a gate insulation layer on the source/drain electrodes; depositing a second metal layer on the gate insulation layer and subjecting the second metal layer to patterning to form a gate electrode;
(7) forming a protection layer on the gate insulation layer and the gate electrode; forming a planarization layer on the protection layer; forming a via in the planarization layer, the protection layer, and the gate insulation layer to correspond to the source/drain electrodes; and
(8) forming a cathode on the planarization layer such that the cathode is connected through the via to the source/drain electrodes; forming a pixel definition layer on the planarization layer and forming an opening in the pixel definition layer to expose a portion of the cathode; conducting vapor depositing of an organic light-emitting diode (OLED) in the opening;
wherein in step (1), the base plate comprises a glass plate;
wherein in step (1), the buffer layer comprises a silicon nit

Assignees

• Shenzhen China Star Optoelect

Inventors

• Zhang Xiaoxing

Classifications

• H10D84/01 Primary

  Manufacture or treatment · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H01L27/1274

  Electricity · mapped topic

• H01L29/66757

  Electricity · mapped topic

• H01L27/3248

  Electricity · mapped topic