Thin film transistor array substrate, organic light-emitting diode display including the same, and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2016133679-A1
Application number	US-201514697018-A
Country	US
Kind code	A1
Filing date	Apr 27, 2015
Priority date	Nov 7, 2014
Publication date	May 12, 2016
Grant date	—

Abstract

A TFT array substrate, OLED display including the same, and a manufacturing method of the OLED display are disclosed. In one aspect, the TFT array substrate includes a substrate and a TFT formed over the substrate. The TFT includes an active layer, a gate electrode, a source electrode, a drain electrode, a first insulating layer interposed between the gate electrode and the source and drain electrodes. Each of the source and drain electrodes is interposed between the active layer and the first insulating layer. The TFT array substrate also includes a capacitor formed over the substrate and having lower and upper electrodes and a pixel electrode electrically connected to the TFT.

First claim

What is claimed is:

1 . A thin film transistor (TFT) array substrate for a display device, the TFT array substrate comprising:
a substrate; a TFT formed over the substrate and comprising an active layer, a gate electrode, a source electrode, a drain electrode, a first insulating layer interposed between the gate electrode and the source and drain electrodes, wherein each of the source and drain electrodes is interposed between the active layer and the first insulating layer; a capacitor formed over the substrate and having lower and upper electrodes; and a pixel electrode electrically connected to the TFT.

2 . The TFT array substrate of claim 1 , wherein the lower electrode of the capacitor is formed of the same material as that of the source and drain electrodes and formed on the same layer as the source and drain electrodes, and
wherein the upper electrode of the capacitor is formed on the same layer as the gate electrode and formed of the same material as that of the gate electrode.

3 . The TFT array substrate of claim 1 , wherein the active layer has a first region at least partially overlapping the source and drain electrodes, a second region at least partially overlapping the gate electrode, and a third region different from the first and second regions, and wherein only the third region includes doped impurities.

4 . The TFT array substrate of claim 3 , wherein the first region includes an area in which the active layer directly contacts the source and drain electrodes.

5 . The TFT array substrate of claim 4 , wherein the first insulating layer covers the active layer, the source electrode and the drain electrode.

6 . The TFT array substrate of claim 5 , wherein the gate electrode is formed over the first insulating layer.

7 . The TFT array substrate of claim 1 , wherein the active layer, the source electrode, and the drain electrode are integrally formed.

8 . The TFT array substrate of claim 1 , further comprising a second insulating layer which is formed over the TFT and the capacitor so as to cover the gate electrode and the upper electrode of the capacitor.

9 . An organic light-emitting diode (OLED) display comprising:
a substrate; a thin film transistor (TFT) formed over the substrate and comprising an active layer, a gate electrode, a source electrode, a drain electrode, a first insulating layer interposed between the gate electrode and the source and drain electrodes, wherein each of the source and drain electrodes are interposed between the active layer and the first insulating layer; a capacitor formed over the substrate and comprising a lower electrode formed on the same layer as the source and drain electrodes and an upper electrode formed on the same layer as the gate electrode; a second insulating layer formed over the TFT and the capacitor so as to cover the gate electrode and the upper electrode; a pixel electrode electrically connected to the TFT; a third insulating layer exposing a central portion of the pixel electrode and covering an edge of the pixel electrode; an intermediate layer formed over the pixel electrode and comprising an emission layer; and an opposite electrode covering the intermediate layer and facing the pixel electrode.

10 . The OLED display of claim 9 , wherein the active layer has a first region at least partially overlapping the source and drain electrodes, a second region at least partially overlapping the gate electrode, and a third region different from the first and second regions, and wherein only the third region includes doped impurities.

11 . A method of manufacturing an organic light-emitting diode (OLED) display, the method comprising:
first forming a semiconductor material layer and a first metal layer over a substrate, wherein the first metal layer is formed over the semiconductor material layer; first patterning the semiconductor material layer and the first metal layer so as to form an active layer, a source electrode, and a drain electrode of a thin film transistor (TFT); second forming a first insulating layer including a portion corresponding to the active layer; third forming a second metal layer over the active layer, the source electrode and the drain electrode; second patterning the second metal layer so as to form a gate electrode on the portion of the first insulating layer; fourth forming a second insulating layer, having a via hole, over the first insulating layer so as to cover the gate electrode, wherein the via hole exposes one of the source and drain electrodes; fifth forming a third metal layer over the second insulating layer; third patterning the third metal layer so as to form a pixel electrode electrically connected to one of the source and drain electrodes through the via hole; and sixth forming a third insulating layer over the second insulating layer so as to cover edges of the pixel electrode and expose the remaining portion of the pixel electrode.

12 . The method of claim 11 , wherein the first forming and the first patterning are performed with a first mask,
wherein the second forming, the third forming and second patterning are performed with a second mask, wherein the fourth forming is performed with a third mask, wherein the fifth forming and the fifth patterning are performed with a fourth mask, and wherein the sixth forming is performed with a fifth mask.

13 . The method of claim 11 , wherein the first forming comprises forming a lower electrode of a capacitor over the substrate.

14 . The method of claim 13 , wherein, in the first forming, the lower electrode of the capacitor is formed on the same layer as the source and drain electrodes, and formed substantially simultaneously as the source and drain electrodes.

15 . The method of claim 11 , wherein the second forming further comprises forming an upper electrode of the capacitor over the lower electrode.

16 . The method of claim 15 , wherein, in the second forming, the upper electrode of the capacitor is formed on the same layer as that of the gate electrode and formed substantially simultaneously as the gate electrode.

17 . The method of claim 11 , wherein the first forming is performed with a half-tone mask.

18 . The method of claim 11 , wherein the active layer, the source electrode, and the drain electrode are integrally formed.

19 . The method of claim 11 , wherein the active layer has a first region at least partially overlapping the source and drain electrodes, a second region at least partially overlapping the gate electrode, and a third region different from the first and second regions, and wherein the first region is formed such that the active layer directly contacts the source and drain electrodes.

20 . The method of claim 19 , further comprising, between the third forming and the fourth forming, forming impurities only in the third region of the active layer.

Assignees

• Samsung Display Co Ltd

Inventors

• Jeon Joohee
• Choi Chaungi
• Yoon Youngsik
• Jung Seungho

Classifications

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/0231 Primary

  using masks, e.g. half-tone masks · CPC title

• H10D30/6729

  characterised by the electrodes · CPC title

• H10D86/481 Primary

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H01L27/1288

  Electricity · mapped topic