Semiconductor chip device

Patent metadata

Field	Value
Publication number	US-9875978-B2
Application number	US-201615292219-A
Country	US
Kind code	B2
Filing date	Oct 13, 2016
Priority date	Oct 16, 2015
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

According to various embodiments, a method may include: forming a first layer on a surface using a first lift-off process; forming a second layer over the first layer using a second lift-off process; wherein the second lift-off process is configured such that the second layer covers at least one sidewall of the first layer at least partially.

First claim

What is claimed is:

1. A semiconductor chip device, comprising:
a substrate;
a contact pad formed over the substrate, wherein the contact pad includes,
a first layer, and
a second layer formed over the first layer, wherein the second layer covers at least one sidewall of the first layer at least partially,

wherein a material of first layer is a material of the second layer.

2. The semiconductor chip device of claim 1 , wherein at least one of the first layer and the second layer comprises a noble metal.

3. The semiconductor chip device of claim 1 ,
wherein at least one of the first layer and the second layer comprises an electrically conductive material.

4. The semiconductor chip device of claim 1 ,
wherein at least one of the first layer and the second layer comprises an electrically insulating material.

5. The semiconductor chip device of claim 1 ,
wherein at least one of the first layer and the second layer comprises at least one of: titanium, platinum, tungsten, gold, aluminum, copper, silver, chromium, and palladium.

6. A semiconductor chip device, comprising:
a substrate;
a contact pad formed over the substrate, wherein the contact pad includes,
a first layer,
a second layer formed over the first layer, wherein the second layer covers at least one sidewall of the first layer at least partially, and
a third layer formed between the first layer and the second layer;

wherein the second layer comprises a noble metal and the third layer comprises a noble metal.

7. The semiconductor chip device of claim 6 ,
wherein the third layer covers only a top surface of the first layer at least partially.

8. The semiconductor chip device of claim 6 , further comprising:
a fourth layer formed between the substrate and the first layer.

9. The semiconductor chip device of claim 8 ,
wherein the third layer is in direct physical contact with the at least one sidewall of the fourth layer.

10. The semiconductor chip device of claim 8 ,
wherein at least one of the third layer and the fourth layer is electrically connected with the second layer.

11. The semiconductor chip device of claim 8 ,
wherein the second layer is in direct physical contact with the at least one sidewall of at least one of the third layer and the fourth layer.

12. The semiconductor chip device of claim 8 ,
wherein the fourth layer comprises at least one of platinum, titanium, chromium, and tungsten; and wherein the second layer comprises gold and the third layer comprises at least one of gold and aluminum.

13. The semiconductor chip device of claim 1 ,
wherein the second layer comprises at least one sidewall that is inclined with respect to a surface of the substrate facing the contact pad by an angle in the range from about 70° to about 85°.

14. The semiconductor chip device of claim 13 ,
wherein the first layer comprises at least one sidewall that is inclined with respect to a surface of the substrate facing the contact pad by an angle in the range from about 70° to about 85°.

15. The semiconductor chip device of claim 1 , wherein the second layer completely covers the least one sidewall of the first layer and further contacts a surface of the substrate facing the contact pad.

16. A semiconductor chip device, comprising:
a substrate;
a contact pad formed over the substrate, wherein the contact pad includes,
a first layer, and
a second layer formed over the first layer, wherein the second layer covers at least one sidewall of the first layer at least partially,

wherein the first layer comprises a non-noble metal and the second layer comprises a noble metal.

17. The semiconductor chip device of claim 6 ,
wherein the second layer covers at least one sidewall of the third layer at least partially.

Assignees

• Infineon Technologies Ag

Inventors

• Gatterbauer Johann
• Weidgans Bernhard
• Bonart Dietrich
• Gross Thomas
• Debie Martina

Classifications

• H10W72/01955

  by using masks · CPC title

• H10W72/352

  comprising metals or metalloids, e.g. solders · CPC title

• H10W72/013

  of die-attach connectors · CPC title

• H10W72/90 Primary

  Bond pads, in general · CPC title

• H10P76/202 Primary

  for lift-off processes · CPC title