Processing techniques for silicon-based transient devices

Patent metadata

Field	Value
Publication number	US-9875974-B2
Application number	US-201414772354-A
Country	US
Kind code	B2
Filing date	Mar 6, 2014
Priority date	Mar 8, 2013
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

Provided are methods of making a transient electronic device by fabricating one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components supported by a mother substrate. The components may independently comprise a selectively transformable material and, optionally, further have a preselected transience profile. The components are transfer printed, thereby decoupling the component fabrication step from additional processing to provide desired device functionality and transient properties. A substrate layer is provided on top of the components and used to facilitate handling, processing, and/or device functionality.

First claim

We claim:

1. A method of making a transient electronic device comprising the steps of:
fabricating one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components on a silicon-on-insulator (SOI) wafer; wherein the one or more inorganic semiconductor components or one or more metallic conductor components independently comprise a selectively transformable material and have a preselected transience profile;
providing a handle substrate having a receiving surface; wherein the receiving surface supports a release layer;
transfer printing the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components from at least a portion of the SOI wafer to the release layer supported by the handle substrate;
removing the release layer on said handle substrate;
providing a substrate layer on top of the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components;
releasing the substrate layer and the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components from the handle substrate;
flipping the substrate layer and the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components to access an exposed surface of said one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components supported by the substrate layer; and
processing the exposed surface, thereby making said transient electronic device;
wherein the SOI wafer comprises: a silicon handle wafer having a <111> orientation; a buried insulator layer; and a top layer of active Si having a <100> orientation from which the one or more semiconductor components are formed.

2. The method of claim 1 , wherein said step of fabricating one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components supported by an SOI wafer is carried out at a semiconductor foundry.

3. The method of claim 1 , wherein said steps other than said step of fabricating one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components supported by an SOI wafer are not carried out in a semiconductor foundry.

4. The method of claim 1 , wherein the processing step comprises adding a transient device component.

5. The method of claim 4 , wherein the transient device component comprises an electrode, an electrical interconnect, a semiconductor, an encapsulating layer, or any combination thereof.

6. The method of claim 1 , wherein the processing step further comprises modifying a physical parameter of the inorganic semiconductor component or metallic conductor component to make a corresponding transient inorganic semiconductor component or transient metal conductor component.

7. The method of claim 6 , wherein the physical parameter is one or more of:
porosity, thickness, effective density, defect density, dopant concentration, composition, or morphology.

8. The method of claim 1 , wherein the processing step comprises providing a transient substrate.

9. The method of claim 1 , wherein the processing step comprises encapsulating at least a portion of the exposed surface with an encapsulating layer.

10. The method of claim 9 , wherein the encapsulating layer comprises a selectively removable material that is at least partially removed in response to an external or internal stimulus.

11. The method of claim 10 , wherein the selectively removable material of the encapsulating layer comprises a material selected from the group consisting of a polymer, a metal, a metal oxide, a glass and a ceramic.

12. The method of claim 9 , wherein the encapsulating layer, the substrate and at least a portion of the one or more inorganic semiconductor components or the one or more metallic conductor components, each independently comprise a selectively transformable material.

13. The method of claim 1 , wherein processing the exposed surface comprises providing one or more interconnect structures for electrically interconnecting the one or more semiconductor components, wherein the interconnect structures independently comprise a selectively transformable material and have a preselected transience profile.

14. The method of claim 1 , further comprising the step of integrating a transient passive component, a transient active component, or both, with the one or more inorganic semiconductor components.

15. The method of claim 14 , wherein the integrating step is carried out after the step of flipping the substrate layer.

16. The method of claim 14 , wherein the integrating step is part of the fabricating step.

17. The method of claim 1 further comprising providing a protective layer between said release layer and said one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components.

18. The method of claim 17 , wherein said protective layer allows for said removal of said release layer without substantial degradation of said one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components.

19. The method of claim 17 wherein said protective layer is a polymer layer in contact with said one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components.

20. The method of claim 1 , wherein the fabricating step comprises forming a plurality of semiconductor components on the SOI wafer.

21. The method of claim 20 , wherein the fabricating step further comprises undercutting the semiconductor components.

22. The method of claim 21 , wherein the plurality of semiconductor components are freestanding on the SOI wafer and connected to the SOI wafer by one or more anchors.

23. The method of claim 1 , further comprising the step of: etching the Si <111> handle wafer to facilitate release of the one or more semiconductor device components that comprise Si <100> from the SOI wafer.

24. The method of claim 1 , wherein the SOI wafer comprises a commercial quality SOI wafer that is coated with the buried insulator layer that is an oxide layer, and the oxide layer is bonded to a bulk <111>-oriented silicon wafer.

25. The method of claim 24 , wherein the oxide layer comprises silicon dioxide.

26. The method of claim 1 , wherein the transfer printing comprises dry transfer contact printing.

27. The method of claim 26 , wherein the dry transfer printing further comprises
contacting the one or m

Assignees

• Univ Illinois

Inventors

• Rogers John A
• Hwang Sukwon
• Huang Xian

Classifications

• H10P72/7436

  used to support a device or a wafer when forming electrical connections thereto · CPC title

• H10P72/7434

  used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate · CPC title

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title