Semiconductor device components and methods

Patent metadata

Field	Value
Publication number	US-9875964-B2
Application number	US-201414166686-A
Country	US
Kind code	B2
Filing date	Jan 28, 2014
Priority date	Sep 13, 2011
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.

First claim

What is claimed is:

1. A device, comprising:
a first conductive line in a first metal layer, the first conductive line having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end;
a first via landing on the first surface of the first conductive line adjacent the first end;
a second via landing on the second surface of the first conductive line adjacent the first end;
a third via landing on the first surface of the first conductive line adjacent the second end; and
a second conductive line in a second metal layer, wherein one of the first via and the third via lands on the second conductive line, wherein the first conductive line, the second conductive line, the first via, the second via, and the third via are disposed on a scribe line of a semiconductor wafer.

2. The device of claim 1 , further comprising:
a fourth via landing on the second surface of the first conductive line adjacent the second end.

3. The device of claim 2 , further comprising:
a third conductive line in a third metal layer, wherein one of the second via and the fourth via lands on the third conductive line.

4. The device of claim 2 , wherein the first via lands on the second conductive line, and further comprising:
a third conductive line in a third metal layer, wherein the second via lands on the third conductive line;
a fourth conductive line in the second metal layer, wherein the third via lands on the fourth conductive line; and
a fifth conductive line in the third metal layer, wherein the fourth via lands on the fifth conductive line.

5. The device of claim 4 , further comprising:
a first contact pad, the second conductive line terminating on the first contact pad;
a second contact pad, the third conductive line terminating on the second contact pad;
a third contact pad, the fourth conductive line terminating on the third contact pad; and
a fourth contact pad, the fifth conductive line terminating on the fourth contact pad.

6. The device of claim 1 , wherein:
the first conductive line has a first length extending in a first direction from the first end to the second end, and a first width extending in a second direction orthogonal to the first direction, wherein the first width is a minimum feature size of the device.

7. The device of claim 6 , wherein the second conductive line has a second width, the second width being at least twice the first width.

8. The device of claim 6 , wherein the first via has first diameter, the first diameter being substantially equal to the first width.

9. A device, comprising:
a conductive line having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end;
a first via coupled to the first surface of the conductive line at the first end;
a second via coupled to the second surface of the conductive line at the first end;
a third via coupled to the first surface of the conductive line at the second end; and
a fourth via coupled to the second surface of the conductive line at the second end, wherein the conductive line, the first via, the second via, the third via, and the fourth via are disposed on a scribe line of a semiconductor wafer, disposed on a dedicated test integrated circuit of a semiconductor wafer, or disposed on a functional integrated circuit.

10. The device according to claim 9 , wherein the conductive line comprises a fuse.

11. The device according to claim 9 , wherein the second via is coupled to the second surface of the conductive line proximate the first via, and wherein the fourth via is coupled to the second surface of the conductive line proximate the third via.

12. The device according to claim 9 , wherein the first via is disposed directly over the second via above the conductive line, and wherein the third via is disposed directly over the fourth via above the conductive line.

13. The device according to claim 9 , wherein the conductive line comprises a first width, and wherein the first via, the second via, the third via, and the fourth via comprise substantially the first width on at least a portion thereof.

14. A fuse comprising:
a fuse element in a first metal layer, the fuse element having a top surface and a bottom surface, and having a first length extending from a first end to a second end, and a first width extending orthogonal to the first length;
a first via contacting the top surface of the fuse element at the first end and extending from the first metal layer to an overlying metal layer;
a second via contacting the bottom surface of the fuse element at the first end and extending from the first metal layer to an underlying metal layer, wherein a first width of the second via decreases as the second via extends from the first metal layer to an underlying metal layer;
a third via contacting the top surface of the fuse element at the second end and extending from the first metal layer to the overlying metal layer, wherein a second width of at least one of the first via and the third via increases as the first via and the third via extend from the first metal layer to the overlying metal layer;
a first conductive element in the overlying metal layer electrically coupling the first end of the fuse to a first contact pad;
a second conductive element in the underlying metal layer electrically coupling the second end of the fuse to a second contact pad; and
a third conductive element in the overlying metal layer electrically coupling the second end of the fuse to a third contact pad,
wherein each of the first conductive element, the second conductive element, and the third conductive element has a width that is greater than the first width,
wherein the first contact pad, the second contact pad, and the third contact pad are different contact pads; and
wherein the first contact pad, the second contact pad and the third contact pad are in a same metal layer.

15. The fuse of claim 14 , further comprising:
a fourth via contacting the bottom surface of the fuse element at the second end and extending from the first metal layer to the underlying metal layer; and
a fourth conductive element in the underlying metal layer electrically coupling the first end of the fuse to a first contact pad.

16. The fuse of claim 15 , wherein the fuse can be programmed from a conductive state to a non-conductive state by supplying programming current through a path selected from the group consisting of the first via to the third via, the first via to the fourth via, the second via to the third via, the second via to the fourth via, and combinations thereof.

17. The device of claim 1 , wherein the first conductive line is a fuse link of an electrically programmed fuse (eFuse).

18. The fuse of claim 14 , wherein the first width is between about 0.01 μm and about 0.1 μm.

19. The fuse of claim 15 , wherein a third width of the fourth via decreases as the fourth via extends from the first metal layer to an underlying metal layer.

20. The device of claim 1 , wherein at least one of the first via, the second via, and the third via comprises a substantially annular barrier layer surrounding a substantially circular shaped copper conductor.

21. The device of claim 20 , wherein:
at least one of the first via and the third via has a first diameter at a first end proximate the first conductive line and a second diameter at a second end proximate the second metal layer, wherein the second diameter is greater than the first diameter; an

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Bi-Ling
• Lin Jian-Hong
• Hsieh Ming-Hong
• Chen Lee-Der
• Shih Jiaw-Ren
• Chiu Chwei-Ching

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/493 Primary

  Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title

• G01R31/2884

  using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence) · CPC title

• G01R31/2858

  Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection · CPC title