Semiconductor device

Patent metadata

Field	Value
Publication number	US-9875963-B2
Application number	US-201514848810-A
Country	US
Kind code	B2
Filing date	Sep 9, 2015
Priority date	Dec 19, 2014
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

According to one embodiment, an integrated circuit is formed on a semiconductor chip, a regulator supplies power to the integrated circuit via the power-supply wire, a first resistor is connected between the first pad electrode and the power-supply wire on the semiconductor chip, and a second resistor is connected between the second pad electrode and the power-supply wire on the semiconductor chip and has a resistance smaller than that of the first resistor.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an integrated circuit formed on a semiconductor chip;
a first pad electrode formed on the semiconductor chip;
a second pad electrode formed on the semiconductor chip;
a third pad electrode formed on the semiconductor chip;
a power-supply wire formed on the semiconductor chip;
a regulator that supplies a power-supply voltage to the integrated circuit via the power-supply wire;
a first resistor that is connected between the first pad electrode and the power-supply wire and sets a resistance between the first pad electrode and the power-supply wire to a first resistance;
a second resistor that is connected between the second pad electrode and the power-supply wire and sets a resistance between the second pad electrode and the power-supply wire to a second resistance smaller than the first resistance; and
a third resistor that is connected between the third pad electrode and the power-supply wire and sets a resistance between the third pad electrode and the power-supply wire to a third resistance larger than the second resistance,
wherein the integrated circuit and the regulator are formed on the same semiconductor chip,
the first pad electrode and the third pad electrode are connected together via a first wire, the first wire being located outside of the semiconductor chip, and
the first pad electrode and the third pad electrode are respectively usable to take out an output of the regulator to the first wire.

2. The semiconductor device according to claim 1 , further comprising:
a package that seals the semiconductor chip;
and
a second wire that is connected to the second pad electrode and is formed on the package, wherein
the first pad electrode is not electrically connected to the second pad electrode, and
the first wire is formed on the package.

3. The semiconductor device according to claim 1 , further comprising:
a fourth pad electrode formed on the semiconductor chip; and
a fourth resistor that is connected between the fourth pad electrode and the power-supply wire and sets a resistance between the fourth pad electrode and the power-supply wire to a fourth resistance smaller than the first resistance and smaller than the third resistance,
wherein
the first resistor, the second resistor, the third resistor, and the fourth resistor are connected to the power-supply wire, and
the second pad electrode and the fourth pad electrode are connected together via a second wire, the second wire being located outside of the semiconductor chip.

4. The semiconductor device according to claim 2 ,
wherein the package includes:
a first terminal connected to the first wire; and
a second terminal connected to the second wire.

5. The semiconductor device according to claim 4 , further comprising:
a wiring substrate on which the package is implemented; and
a capacitor that is implemented on the wiring substrate and is connected to the first terminal.

6. The semiconductor device according to claim 2 , wherein the package includes a capacitor connected to the first pad electrode.

7. The semiconductor device according to claim 1 , further comprising:
a wiring substrate on which the semiconductor chip is implemented;
a second wire that is connected to the second pad electrode and is formed on the wiring substrate; and
a capacitor connected to the first wire, wherein
the first wire is formed on the wiring substrate.

8. The semiconductor device according to claim 1 ,
wherein at least the first resistor is a parasitic resistor of a wire connecting the first pad electrode and the power-supply wire, and
the second resistor is a parasitic resistor of a wire connecting the second pad electrode and the power-supply wire.

9. The semiconductor device according to claim 1 , wherein the regulator includes:
a transistor connected between a regulator power supply and the power-supply wire; and
an amplifier that controls conduction of the transistor according to output from the regulator, and wherein
the power-supply wire is arranged in a meshed pattern on the semiconductor chip, and
the transistor is distributed around the power-supply wire.

10. A semiconductor device, comprising:
an integrated circuit formed on a semiconductor chip;
a first pad electrode formed on the semiconductor chip;
a second pad electrode formed on the semiconductor chip;
a third pad electrode formed on the semiconductor chip;
a power-supply wire formed on the semiconductor chip;
a regulator that supplies a power-supply voltage to the integrated circuit via the power-supply wire;
a first wire that is connected between the first pad electrode and the power-supply wire and has a first resistance;
a second wire that is connected between the second pad electrode and the power-supply wire and has a second resistance smaller than the first resistance; and
a third wire that is connected between the third pad electrode and the power-supply wire and has a third resistance larger than the second resistance,
wherein the integrated circuit and the regulator are formed on the same semiconductor chip,
the first pad electrode and the third pad electrode are connected together via a fourth wire, the third wire being located outside of the semiconductor chip, and
the first pad electrode and the third pad electrode are respectively usable to take out an output of the regulator to the fourth wire.

11. The semiconductor device according to claim 10 , further comprising:
a package that seals the semiconductor chip;
and
a fifth wire that is connected to the second pad electrode and is formed on the package, wherein
the first pad electrode is not electrically connected to the second pad electrode, and
the fourth wire is formed on the package.

12. The semiconductor device according to claim 10 , further comprising:
a fourth pad electrode formed on the semiconductor chip; and
a fifth wire that is connected between the fourth pad electrode and the power-supply wire and sets a resistance between the fourth pad electrode and the power-supply wire to a fourth resistance smaller than the first resistance and smaller than the third resistance,
wherein
the first wire, the second wire, the third wire, and the fifth wire are connected to the power-supply wire, and
the second pad electrode and the fourth pad electrode are connected together via a sixth wire, the sixth wire being located outside of the semiconductor chip.

13. The semiconductor device according to claim 11 ,
wherein the package includes:
a first terminal connected to the fourth wire; and
a second terminal connected to the fifth wire.

14. The semiconductor device according to claim 13 , further comprising:
a wiring substrate on which the package is implemented; and
a capacitor that is implemented on the wiring substrate and is connected to the first terminal.

15. The semiconductor device according to claim 11 ,
wherein the package includes a capacitor connected to the first pad electrode.

16. The semiconductor device according to claim 10 , further comprising:
a wiring substrate on which the semiconductor chip is implemented;
a fifth wire that is connected to the second pad electrode and is formed on the wiring substrate; and
a capacitor connected to the fourth wire in the wiring substrate, wherein
the fourth wire is formed on the wiring substrate.

17. The semiconductor device according to claim 10 ,
wherein at least the first resistance is a resistance of a parasitic resistor of the first wire, and
the second resistance is a res

Assignees

• Toshiba Memory Corp

Inventors

• Kushibe Hidefumi
• Ideno Hiroyuki
• Usuda Masayuki

Classifications

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/498 Primary

  Resistive arrangements or effects of, or between, wiring layers · CPC title

• G05F3/02

  Regulating voltage or current · CPC title

• H01L23/5223

  Electricity · mapped topic

• H01L23/5228 Primary

  Electricity · mapped topic