Method of packaging a circuit

Patent metadata

Field	Value
Publication number	US-9875930-B2
Application number	US-201414582349-A
Country	US
Kind code	B2
Filing date	Dec 24, 2014
Priority date	Sep 23, 2011
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

Methods of packaging integrated circuits are disclosed herein. In one embodiment of a method. A die having a side is provided. A conductive stud is connected to the side of the die, wherein the conductive stud has a first end that is connected to the die and an opposite second end. The die is encapsulated except for the side. A first dielectric layer is affixed to the side of the die. The first dielectric layer has a first side and a second side. The first side of the first dielectric layer is affixed to the side of the die. The conductive stud enters the first side of the first dielectric layer. A conductive layer is affixed to the second side of the first dielectric layer. The second side of the conductive stud is affixed to the conductive layer using a conductive adhesive.

First claim

What is claimed is:

1. A method for packaging an integrated circuit (IC), comprising:
encapsulating a die having a side, with an encapsulant, except for the side;
connecting a first end of a conductive stud to the side;
affixing a conductive adhesive on an opposite second end of the conductive stud; and
simultaneously affixing a first dielectric layer to the side of the die and to a portion of the encapsulant, a sum of heights of the conductive stud and the conductive adhesive being less than or approximately equal to a height of the first dielectric layer.

2. The method of claim 1 further comprising:
affixing a conductive layer to the conductive adhesive; and
affixing a second dielectric layer to the first dielectric layer, the second dielectric layer encompassing the conductive layer.

3. The method of claim 1 , wherein affixing a first dielectric layer comprises affixing a partially cured first dielectric layer.

4. The method of claim 1 , wherein encapsulating the die with the encapsulant comprises encapsulating the die with a partially cured encapsulant.

5. The method of claim 2 further comprising electrically connecting solder balls to a set of vias in the second dielectric layer.

6. The method of claim 2 further comprising curing the encapsulant and the first dielectric layer.

7. The method of claim 2 further comprising curing the encapsulant and the first dielectric layer simultaneously.

8. The method of claim 1 , wherein attaching a conductive stud to the side comprises:
attaching a conductive pad to the side; and
attaching the conductive stud to the conductive pad.

9. The method of claim 8 , wherein sum of heights of the conductive stud, the conductive adhesive, and the conductive pad is less than or approximately equal to the height of the first dielectric layer.

10. The method of claim 1 , wherein the height of the first dielectric layer is in between 10 and 50 microns.

11. The method of claim 1 , wherein the height of the conductive stud is in between 10 and 50 microns.

12. A method for packaging an integrated circuit (IC), comprising:
encapsulating a die having a side, with an encapsulant, except for the side;
electrically connecting a first end of a conductive stud to the die;
affixing solder on an opposite second end of the conductive stud; and
simultaneously affixing a first dielectric layer to the side of the die and to a portion of the encapsulant, a sum of heights of the solder and the conductive stud being less than or approximately equal to a height of the first dielectric layer.

13. The method of claim 12 further comprising:
affixing a conductive layer to the solder; and
affixing a second dielectric layer to the first dielectric layer, the second dielectric layer encompassing the conductive layer.

14. The method of claim 13 further comprising electrically connecting solder balls to the conductive layer.

15. The method of claim 12 , wherein the first dielectric layer is a non-fibrous dielectric material.

16. The method of claim 13 , wherein the conductive layer is a metal foil.

17. A method for packaging an integrated circuit (IC), comprising:
encapsulating a die having a side, with an encapsulant, except for the side;
affixing a conductive pad to the side;
connecting a first end of a conductive stud to the conductive pad;
affixing conductive adhesive on an opposite second end of the conductive stud;
simultaneously affixing a first dielectric layer to the side of the die and to a portion of the encapsulant, a sum of heights of the conductive pad, the conductive stud, the conductive adhesive being less than or approximately equal to a height of the first dielectric layer;
affixing a conductive layer to the conductive adhesive; and
affixing a second dielectric layer to the first dielectric layer, the second dielectric layer encompassing the conductive layer.

Assignees

• Texas Instruments Inc

Inventors

• Gallegos Bernardo
• Castro Abram

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title