Self-aligned shielding of silicon oxide

US9875907B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9875907-B2
Application numberUS-201615235048-A
CountryUS
Kind codeB2
Filing dateAug 11, 2016
Priority dateNov 20, 2015
Publication dateJan 23, 2018
Grant dateJan 23, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

Methods of etching silicon nitride faster than silicon oxide are described. Exposed portions of silicon nitride and silicon oxide may both be present on a patterned substrate. A self-assembled monolayer (SAM) is selectively deposited over the silicon oxide but not on the exposed silicon nitride. Molecules of the self-assembled monolayer include a head moiety and a tail moiety, the head moiety forming a bond with the OH group on the exposed silicon oxide portion and the tail moiety extending away from the patterned substrate. A subsequent gas-phase etch using anhydrous vapor-phase HF may then be used to selectively remove silicon nitride much faster than silicon oxide because the SAM has been found to delay the etch and reduce the etch rate.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method of removing silicon nitride from a patterned substrate, the method comprising: (i) selectively forming a partial layer over silicon oxide portions of the patterned substrate but not over silicon nitride portions of the patterned substrate, wherein the partial layer is patterned after formation without applying any form of lithography; and (ii) selectively etching the silicon nitride from the silicon nitride portions faster than silicon oxide from the silicon oxide portions; wherein operation ( 1 ) and operation (ii) occur concurrently and operation ( 1 ) and (ii) are repeated an integral number of times. 2. The method of claim 1 wherein selectively etching the silicon nitride occurs without an application of lithography. 3. The method of claim 1 wherein operation (i) and operation (ii) occur concurrently. 4. A method of etching silicon nitride from a patterned substrate, the method comprising: providing a patterned substrate having an exposed silicon nitride portion and an exposed silicon oxide portion; exposing the patterned substrate to an alkylsilane precursor; forming a self-assembled monolayer on the exposed silicon oxide portion but not on the exposed silicon nitride portion; exposing the patterned substrate to a halogen-containing precursor; etching the silicon nitride from the exposed silicon nitride portion at a silicon nitride etch rate while removing silicon oxide from the exposed silicon oxide portion at a silicon oxide etch rate less than one percent of the silicon nitride etch rate. 5. The method of claim 4 further comprising removing the self-assembled monolayer after etching the silicon nitride. 6. The method of claim 4 wherein forming the self-assembled monolayer occurs before etching the silicon nitride. 7. The method of claim 4 wherein exposing the patterned substrate to the alkylsilane precursor occurs concurrently with exposing the patterned substrate to the halogen-containing precursor. 8. The method of claim 4 wherein forming the self-assembled monolayer and etching the silicon nitride both occur while the patterned substrate is in a plasma-free substrate processing region. 9. The method of claim 4 wherein the halogen-containing precursor comprises fluorine. 10. The method of claim 4 wherein the halogen-containing precursor comprises anhydrous HF. 11. The method of claim 4 wherein the halogen-containing precursor is a gas-phase precursor. 12. The method of claim 4 wherein each molecule of the self-assembled monolayer includes a head moiety and a tail moiety, the head moiety forming a covalent bond with the exposed silicon oxide portion and the tail moiety extending away from the patterned substrate. 13. A method of selectively depositing an additional layer onto a patterned substrate, the method comprising: providing a patterned substrate having an exposed silicon nitride portion and an exposed silicon oxide portion; selectively forming a self-assembled monolayer on the exposed silicon oxide portion but not on the exposed silicon nitride portion; exposing the patterned substrate to a deposition precursor; depositing additional material onto the exposed silicon nitride portion at least one hundred times faster than onto the exposed silicon oxide portion. 14. The method of claim 13 wherein depositing the additional material occurs after selectively forming the self-assembled monolayer. 15. The method of claim 13 wherein selectively forming the self-assembled monolayer and depositing additional material onto the exposed silicon nitride portion each occur while the patterned substrate is in a plasma-free substrate processing region.

Assignees

Inventors

Classifications

  • Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

  • characterised by the processes involved to create the masks · CPC title

  • using masks for insulating materials · CPC title

  • the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

  • the material being a silicon oxide, e.g. SiO2 · CPC title

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What does patent US9875907B2 cover?
Methods of etching silicon nitride faster than silicon oxide are described. Exposed portions of silicon nitride and silicon oxide may both be present on a patterned substrate. A self-assembled monolayer (SAM) is selectively deposited over the silicon oxide but not on the exposed silicon nitride. Molecules of the self-assembled monolayer include a head moiety and a tail moiety, the head moiety f…
Who is the assignee on this patent?
Applied Materials Inc
What technology area does this patent fall under?
Primary CPC classification H10P50/283. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 23 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).