Mechanisms for forming patterns using multiple lithography processes

Patent metadata

Field	Value
Publication number	US-9293341-B2
Application number	US-201414457282-A
Country	US
Kind code	B2
Filing date	Aug 12, 2014
Priority date	Mar 13, 2014
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer formed over the substrate; forming a first feature in a first hard mask layer formed over the patterning-target layer; forming a second feature in a second hard mask layer formed over the patterning-target layer, the first hard mask layer having a different etching selectivity from the second hard mask layer; selectively removing a portion of the first feature in the first hard mask layer within a first trench to formed a reshaped first feature; selectively removing a portion of the second feature in the second hard mask layer within a second trench to form a reshaped second feature; and transferring the reshaped first feature and the reshaped second feature to the patterning-target layer.

First claim

What is claimed is:

1. A method for forming patterns in a semiconductor device, comprising:
providing a substrate and a patterning-target layer formed over the substrate;
forming a first feature in a first hard mask layer formed over the patterning-target layer;
forming a second feature in a second hard mask layer formed over the patterning-target layer, the first hard mask layer having a different etching selectivity from the second hard mask layer;
selectively removing a portion of the first feature within a first trench, thereby forming a reshaped first feature;
selectively removing a portion of the second feature within a second trench, thereby forming a reshaped second feature; and
transferring the reshaped first feature and the reshaped second feature to the patterning-target layer.

2. The method of claim 1 , wherein the forming the first feature in the first hard mask layer includes:
forming the first hard mask layer over the patterning-target layer;
forming a first resist layer over the first hard mask layer;
patterning the first resist layer to form the first feature; and
etching the first hard mask layer using the first resist layer as an etching mask.

3. The method of claim 1 , wherein the forming the second feature in the second hard mask layer includes:
forming a first buffer layer over the first hard mask layer;
etching the first buffer layer to form a third trench;
forming the second hard mask layer to fill the third trench and to cover the first buffer layer; and
removing an upper portion of the second hard mask layer to form the second feature in the second hard mask layer.

4. The method of claim 3 , further comprising:
forming a second resist layer over the first buffer layer;
patterning the second resist layer to form the third trench; and
etching the first buffer layer using the second resist layer as an etching mask.

5. The method of claim 3 , wherein a thickness of the second hard mask layer after removing the upper portion is substantially similar to a thickness of the first hard mask layer.

6. The method of claim 1 , wherein a spacing between the first feature and the second feature is less than a minimum value based on the design rules.

7. The method of claim 1 , further comprising:
forming a third resist layer over the first hard mask layer and the second hard mask layer; and
patterning the third resist layer to form the first trench.

8. The method of claim 7 , wherein the selectively removing the portion of the first feature in the first hard mask layer within the first trench includes:
etching the first hard mask layer using the third resist layer as an etching mask,
wherein the second hard mask layer remains unetched.

9. The method of claim 7 , further comprising:
forming a second buffer layer between the third resist layer and the first hard mask layer and the second hard mask layer; and
etching the second buffer layer using the third resist layer as an etching mask.

10. The method of claim 1 , further comprising:
forming a fourth resist layer over the first hard mask layer and the second hard mask layer; and
patterning the fourth resist layer to form the second trench.

11. The method of claim 10 , wherein the selectively removing the portion of the second feature in the second hard mask layer within the second trench includes:
etching the second hard mask layer using the fourth resist layer as an etching mask,
wherein the first hard mask layer remains unetched.

12. The method of claim 10 , further comprising:
forming a third buffer layer between the fourth resist layer and the first hard mask layer and the second hard mask layer; and
etching the third buffer layer using the fourth resist layer as an etching mask.

13. The method of claim 1 , wherein the transferring the reshaped first feature and the reshaped second feature to the patterning-target layer includes:
etching the patterning-target layer using the first hard mask layer and the second hard mask layer as etching masks.

14. The method of claim 1 , wherein a spacing between a removed portion of the first feature and a removed portion of the second feature is less than a minimum value based on the design rules.

15. A method for forming patterns in a semiconductor device, comprising:
providing a substrate, a patterning-target layer formed over the substrate, and a first hard mask layer formed over the patterning-target layer;
performing a first lithography to form a first feature in the first hard mask layer, the first hard mask layer including a first material;
forming a buffer layer over the first hard mask layer;
performing a second lithography to form a first trench in the buffer layer;
forming a second feature in the first trench using a second hard mask layer, the second hard mask layer including a second material;
forming a first resist layer over the first hard mask layer and the second hard mask layer;
performing a third lithography to form a second trench in the first resist layer;
etching the first hard mask layer within the second trench using the first resist layer as an etching mask;
forming a second resist layer over the first hard mask layer and the second hard mask layer;
performing a fourth lithography to form a third trench in the second resist layer;
etching the second hard mask layer within the third trench using the second resist layer as an etching mask; and
etching the patterning-target layer using the first hard mask layer and the second hard mask layer as etching masks.

16. The method of claim 15 , wherein the first material includes titanium nitride, and
wherein the second material includes one or more materials selected from the group consisting of silicon nitride and silicon oxynitride.

17. The method of claim 15 , wherein the etching the second hard mask layer includes using one or more etching gases selected from the group consisting of carbon tetrafluoride, difluoromethane, and trifluoromethane, and wherein the etching the first hard mask layer includes using chlorine.

18. The method of claim 15 , wherein the performing the first lithography includes:
forming a third resist layer over the first hard mask layer;
patterning the third resist layer to form the first feature; and
etching the first hard mask layer using the first resist layer as an etching mask.

19. The method of claim 15 , wherein the forming the second feature in the first trench using the second hard mask layer includes:
depositing the second hard mask layer to fill in the first trench and to cover the buffer layer; and
removing an upper portion of the second hard mask layer,
wherein a thickness of the second hard mask layer after removing the upper portion is substantially similar to a thickness of the first hard mask layer.

20. A method for forming patterns in a semiconductor device, comprising:
forming a first feature in a first hard mask layer using a first lithography, the first hard mask layer being formed over a patterning-target layer;
forming a second feature in a second hard mask layer using a second lithography, the second hard mask layer being formed over the patterning-target layer, and the first hard mask layer having a different etching selectivity from the second hard mask layer;
forming a first trench in a first material layer formed over the first hard mask layer and the second hard mask layer;
etching a portion of the first hard mask layer exposed within the first trench to define a first trimmed line feature;
forming a second

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Chang Shih-Ming

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/2041

  Photolithographic processes · CPC title

• H10P50/73 Primary

  using masks for insulating materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title