Branching to alternate code based on runahead determination

Patent metadata

Field	Value
Publication number	US-9582280-B2
Application number	US-201313945838-A
Country	US
Kind code	B2
Filing date	Jul 18, 2013
Priority date	Jul 18, 2013
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

The description covers a system and method for operating a micro-processing system having a runahead mode of operation. In one implementation, the method includes providing, for a first portion of code, a runahead correlate. When the first portion of code is encountered by the micro-processing system, a determination is made as to whether the system is operating in the runahead mode. If so, the system branches to the runahead correlate, which is specifically configured to identify and resolve latency events likely to occur when the first portion of code is encountered outside of runahead. Branching out of the first portion of code may also be performed based on a determination that a register is poisoned.

First claim

The invention claimed is:

1. A method of operating a micro-processing system having a runahead mode, comprising:
providing, for a portion of code executable by the micro-processing system, a runahead correlate for the portion of code that is executable by the micro-processing system;
determining, when encountering the portion of code, dynamically and at runtime, whether the micro-processing system is operating in the runahead mode; and
branching to the runahead correlate based upon an affirmative determination that the micro-processing system is operating in the runahead mode when the portion of code is encountered.

2. The method of claim 1 , further comprising:
determining whether a register is poisoned, and wherein branching to the runahead correlate occurs when the micro-processing system is operating in the runahead mode when the portion of code is encountered and the register is poisoned.

3. The method of claim 1 , where the runahead correlate is configured to identify and resolve latency events which potentially will occur when the portion of code is executed outside of runahead.

4. The method of claim 3 , where the latency events are selected from a group consisting of: a load miss, a store miss, a branch mispredict and a TLB miss.

5. The method of claim 1 , wherein the runahead correlate is generated based on a dynamic profiling of the portion of code at runtime.

6. The method of claim 1 , wherein the runahead correlate is an alternate version of the portion of code which omits one or more instructions in the portion of code.

7. The method of claim 1 , wherein the runahead correlate is an alternate version of the portion of code that prioritizes memory operations in the portion of code.

8. The method of claim 1 , wherein the runahead correlate is or contains an instruction to terminate operation in runahead mode, wherein the branching to the runahead correlate causes the micro-processing system to exit runahead.

9. A method of operating a micro-processing system having a runahead mode, comprising:
encountering an instruction within a processing pipeline of the micro-processing system;
executing and generating an output of a condition-testing instruction, the condition-testing instruction being configured to test: (i) whether the micro-processing system is operating in the runahead mode when the instruction is encountered and whether the instruction uses a poisoned register, and
branching out of a portion of code containing the instruction based on the output of the condition-testing instruction.

10. The method of claim 9 , wherein the condition-testing instruction is selectively operable to disable the poison test and provide the runahead test only, wherein the branching out of the portion of code containing the instruction occurs if the runahead test is affirmative, without regard for the poison test.

11. The method of claim 9 , wherein the condition-testing instruction is selectively operable to disable the runahead test and provide the poison test only, wherein the branching out of the portion of code containing the instruction occurs if the poison test is affirmative, without regard for the runahead test.

12. The method of claim 9 , wherein the condition-testing instruction is selectively operable to enable both the runahead test and the poison test, wherein the branching out of the portion of code containing the instruction occurs only if both the runahead test and the poison test are affirmative.

13. The method of claim 9 , further comprising providing a runahead correlate for the portion of code and branching to the runahead correlate when the runahead test is affirmative.

14. The method of claim 13 , wherein the runahead correlate is an alternate version operable to omit instructions of the portion of code and is configurable to identify and resolve latency events which potentially will occur when the portion of code is executed outside of runahead.

15. The method of claim 13 , wherein the runahead correlate is generated based on a dynamic profiling of the portion of code.

16. The method of claim 13 , wherein the runahead correlate is or contains an instruction to terminate operation in runahead mode, wherein the branching to the runahead correlate causes the micro-processing system to exit runahead.

17. A micro-processing system having a runahead mode, comprising:
a memory/storage subsystem;
a processing pipeline configured to retrieve instructions and data from the memory/storage subsystem;
runahead logic included in or operatively coupled with the processing pipeline and operative to cause the micro-processing system to enter the runahead mode upon occurrence of a stall condition in the processing pipeline; and
a portion of code contained in the memory/storage subsystem and executable by the processing pipeline, wherein the processing pipeline is configured, in response to encountering the portion of code, to determine whether the micro-processing system is in the runahead mode and responsive to a determination that the micro-processing system is in the runahead mode to branch to and execute a runahead correlate to the portion of code in lieu of executing the portion of code, wherein the runahead correlate is configured to identify and resolve latency events which potentially will occur when the portion of code is executed outside of runahead.

18. The micro-processing system of claim 17 , wherein the runahead correlate is an alternate version of the portion of code which omits one or more instructions in the portion of code.

19. The micro-processing system of claim 17 , wherein the runahead correlate is an alternate version of the portion of code that prioritizes memory operations in the portion of code.

20. The micro-processing system of claim 17 , wherein the runahead correlate is or contains an instruction to terminate operation in runahead mode, wherein the branching to the runahead correlate causes the micro-processing system to exit runahead.

Assignees

• Nvidia Corp

Inventors

• Kumar Rohit
• Rozas Guillermo
• Ekman Magnus
• Spracklen Lawrence

Classifications

• G06F9/383 Primary

  Operand prefetching (cache prefetching G06F12/0862) · CPC title

• G06F9/3867

  using instruction pipelines · CPC title

• G06F9/30189 Primary

  according to execution mode, e.g. mode flag · CPC title

• G06F9/3865

  using deferred exception handling, e.g. exception flags · CPC title

• G06F9/3842

  Speculative instruction execution · CPC title