Method and system for gas flow mitigation of molecular contamination of optics

US9874512B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9874512-B2
Application numberUS-201414466516-A
CountryUS
Kind codeB2
Filing dateAug 22, 2014
Priority dateFeb 25, 2013
Publication dateJan 23, 2018
Grant dateJan 23, 2018

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Abstract

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A computer-implemented method for determining an optimized purge gas flow in a semi-conductor inspection metrology or lithography apparatus, comprising receiving a permissible contaminant mole fraction, a contaminant outgassing flow rate associated with a contaminant, a contaminant mass diffusivity, an outgassing surface length, a pressure, a temperature, a channel height, and a molecular weight of a purge gas, calculating a flow factor based on the permissible contaminant mole fraction, the contaminant outgassing flow rate, the channel height, and the outgassing surface length, comparing the flow factor to a predefined maximum flow factor value, calculating a minimum purge gas velocity and a purge gas mass flow rate from the flow factor, the contaminant mass diffusivity, the pressure, the temperature, and the molecular weight of the purge gas, and introducing the purge gas into the semi-conductor inspection metrology or lithography apparatus with the minimum purge gas velocity and the purge gas flow rate.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for determining an optimized purge gas flow in a semi-conductor inspection metrology or lithography apparatus, comprising: accepting, using a processor, a first input identifying a position of at least one input port for a semi-conductor inspection metrology or lithography apparatus; or identifying, using a processor, a position of at least one input port for a semi-conductor inspection metrology or lithography apparatus; accepting, using the processor, a second input identifying a position of at least one output port for the semi-conductor inspection metrology or lithography apparatus; or identifying, using the processor, a position of at least one output port for a semi-conductor inspection metrology or lithography apparatus; identifying, using the processor: at least one desorption surface in the semi-conductor inspection metrology or lithography apparatus; a desorption rate associated with the at least one desorption surface; and, a contaminant released from the at least one desorption surface; identifying, using the processor, at least one purge gas flow path, through the semi-conductor inspection metrology or lithography apparatus for a purge gas; calculating, using the processor and the respective identifications of the at least one desorption surface, the desorption rate, and the released contaminant, at least one minimum velocity and flow rate for a flow of purge gas, from the position of the at least one input port across the at least one desorption surface to the position of the at least one output port, sufficient to transport the released contaminant from a vicinity of the at least one desorption surface to the at least one output port; introducing the purge gas into the semi-conductor inspection metrology or lithography apparatus through the at least one input port with the at least one minimum velocity and gas flow rate; and, transporting the released contaminant from the vicinity of the at least one desorption surface to the at least one output port. 2. The method recited in claim 1 , further comprising: identifying, using the processor, a set of channel dimensions within the semi-conductor inspection metrology or lithography apparatus. 3. The method recited in claim 2 , further comprising: calculating, using the processor and the set of channel dimensions, the at least one minimum velocity and flow rate. 4. The method recited in claim 1 , further comprising: determining, using the processor and the respective identifications of the at least one desorption surface, the desorption rate, and the released contaminant, at least one optimal input port position; and, introducing the purge gas at the at least one optimal input port. 5. The method recited in claim 1 , further comprising: determining, using the processor and the respective identifications of the at least one desorption surface, the desorption rate, and the released contaminant, at least one optimal output port position; and, transporting the released contaminant from the vicinity of the at least one desorption surface to the at least one optimal output port. 6. The method of claim 1 , wherein the purge gas is selected from the group consisting of hydrogen and helium. 7. The method of claim 1 , wherein the contaminant is selected from the group consisting of water and hydrocarbon gasses. 8. A system for determining an optimized purge gas flow in a semi-conductor inspection metrology or lithography apparatus, comprising: a processor arranged to: accept a first input identifying a position of at least one input port for a semi-conductor inspection metrology or lithography apparatus; or identifying, using a processor, a position of at least one input port for a semi-conductor inspection metrology or lithography apparatus; accept a second input identifying a position of at least one output port for the semi-conductor inspection metrology or lithography apparatus; or identifying, using the processor, a position of at least one output port for a semi-conductor inspection metrology or lithography apparatus; identify: at least one desorption surface in the semi-conductor inspection metrology or lithography apparatus; a desorption rate associated with the at least one desorption surface; and, a contaminant released from the at least one desorption surface; identify at least one purge gas flow path, through the semi-conductor inspection metrology or lithography apparatus for a purge gas; calculate using, the respective identifications of the at least one desorption surface, the desorption rate and the released contaminant, at least one minimum velocity and flow rate for a flow of purge gas, from the position of the at least one input port across the at least one desorption surface to the position of the at least one output port, sufficient to transport the released contaminant from a vicinity of the at least one desorption surface to the at least one output port; actuate the at least one input port to introduce the purge gas into the semi-conductor inspection metrology or lithography apparatus with the at least one minimum velocity and gas flow rate; and, actuate the at least one output port to receive the purge gas flow and the released contaminant from the vicinity of the at least one desorption surface. 9. The system recited in claim 8 , wherein the processor is arranged to identify a set of channel dimensions within the semi-conductor inspection metrology or lithography apparatus. 10. The system recited in claim 9 , wherein the processor is arranged to calculate the at least one minimum velocity and flow rate using the set of channel dimension. 11. The system recited in claim 8 , wherein the processor is arrange to: determine at least one optimal input port position using the respective identifications of the at least one desorption surface, the desorption rate, and the released contaminant; and, actuate the at least one input port to introduce the purge gas. 12. The system recited in claim 8 , wherein the processor is arrange to: determine, using the respective identifications of the at least one desorption surface, the desorption rate, and the released contaminant, at least one optimal output port position; and, actuate the at least one optimal output port to remove the purge gas and the released contaminant from the semi-conductor inspection metrology or lithography apparatus. 13. The system of claim 8 , wherein the purge gas is selected from the group consisting of hydrogen, helium, and mixed gas containing hydrogen and helium. 14. The system of claim 8 , wherein the contaminant is selected from the group consisting of water, hydrocarbon gasses, acids, bases, inorganics, metal ions, metal hydrides, and silicon containing compounds including siloxanes. 15. A method for determining an optimized purge gas flow in a semi-conductor inspection metrology or lithography apparatus, comprising: receiving, using a processor, respective inputs in the nature of a permissible contaminant mole fraction, an expected contaminant outgassing flow rate associated with a contaminant, a mass diffusivity of the contaminant, an outgassing surface length, a permissible pressure, a permissible temperature, a channel height, and a molecular weight of a purge gas; calculating, using the processor, a flow factor based on the permissible contaminant mole fraction, the expected contaminant outgassing flow rate, the channel height, and the outgassing surface length; comparing, using the processor, the flow factor to a predefined maximum flow factor value; calculating, using the processor, a minimum

Assignees

Inventors

Classifications

  • G01N21/15Primary

    Preventing contamination of the components of the optical system or obstruction of the light path · CPC title

  • Gas blown · CPC title

  • Purge, e.g. exchanging fluid or gas to remove pollutants · CPC title

  • Semiconductor wafers (manufacturing processes per se of semiconductor devices implementing a measuring step H10P74/20) · CPC title

  • Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions · CPC title

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What does patent US9874512B2 cover?
A computer-implemented method for determining an optimized purge gas flow in a semi-conductor inspection metrology or lithography apparatus, comprising receiving a permissible contaminant mole fraction, a contaminant outgassing flow rate associated with a contaminant, a contaminant mass diffusivity, an outgassing surface length, a pressure, a temperature, a channel height, and a molecular weigh…
Who is the assignee on this patent?
Kla Tencor Corp, Nat Tech & Eng Solutions Sandia Llc
What technology area does this patent fall under?
Primary CPC classification G01N21/15. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 23 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).