Phase shifter chip radio frequency self-test

Patent metadata

Field	Value
Publication number	US-9871602-B2
Application number	US-201615244241-A
Country	US
Kind code	B2
Filing date	Aug 23, 2016
Priority date	Jun 17, 2015
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

A method for operating a phase shifter chip RF self-test. The method includes outputting, by control hardware, a first signal from a phased locked loop to a pre-amplifier and an input peak detector, outputting, by the control hardware, a second signal from the pre-amplifier to a device under test, selecting, by the control hardware, a target level, and adjusting, by the control hardware, a pre-amplifier gain of the pre-amplifier to cause the input peak detector value to approximately match the target level. The input peak detector is configured to output an input peak detector value based on the first signal.

First claim

What is claimed is:

1. A method comprising:
outputting, by control hardware, a first signal from a phased locked loop to a pre-amplifier and an input peak detector, wherein the input peak detector is configured to output an input peak detector value based on the first signal;
outputting, by the control hardware, a second signal from the pre-amplifier to a device under test;
selecting, by the control hardware, a target level; and
adjusting, by the control hardware, a pre-amplifier gain of the pre-amplifier to target the input peak detector value to match the selected target level.

2. The method of claim 1 , further comprising:
adjusting, by the control hardware, a precision variable gain adjuster connected to the pre-amplifier; and
measuring an output peak detector value of an output peak detector connected to an output of the device under test.

3. The method of claim 2 , further comprising adjusting, by the control hardware, a device under test gain of the device under test until the output peak detector value matches the selected target level.

4. The method of claim 3 , further comprising:
stopping, by the control hardware, all signals to the pre-amplifier and the device under test;
measuring, by the control hardware, a current input peak detector value of the input peak detector as an input peak detector offset; and
measuring a current output peak detector value of the output peak detector as an output peak detector offset.

5. The method of claim 4 , further comprising determining, by the control hardware, the input peak detector value by subtracting the input peak detector offset from the input peak detector value of the input peak detector.

6. The method of claim 4 , further comprising determining, by the control hardware, the output peak detector value by subtracting the output peak detector offset from the output peak detector value of the output peak detector.

7. The method of claim 4 , further comprising measuring the input peak detector value and output peak detector value with an analog to digital converter.

8. The method of claim 4 , further comprising adjusting, by the control hardware, the precision variable gain adjuster to confirm that the output peak detector value matches the selected target level within a threshold tolerance.

9. A system comprising:
a phased locked loop;
a pre-amplifier in communication with the phased locked loop;
an input peak detector in communication with the pre-amplifier; and
control hardware in communication with the phased lock loop, the pre-amplifier, and the input peak detector, the control hardware configured to:
output a first signal from the phased locked loop to the pre-amplifier and the input peak detector, wherein the input peak detector is configured to output an input peak detector value based on the first signal;
output a second signal from the pre-amplifier to a device under test;
select a target level; and
adjust the pre-amplifier gain of the pre-amplifier to target the input peak detector value to match the selected target level.

10. The system of claim 9 , further comprising:
a precision variable gain adjuster connected to the pre-amplifier; and
an output peak detector connected to an output of the device under test,
wherein the control hardware is further configured to:
adjust the precision variable gain adjuster; and
measure an output peak detector value of the output peak detector.

11. The system of claim 10 , wherein the control hardware is further configured to adjust a device under test gain of the device under test until the output peak detector value matches the selected target level.

12. The system of claim 11 , wherein the control hardware is further configured to: stop all signals to the pre-amplifier and the device under test;
measure a current input peak detector value of the input peak detector as an input peak detector offset;
measure a current output peak detector value of the output peak detector as an output peak detector offset;
determine input peak detector value by subtracting the input peak detector offset from the input peak detector value of the input peak detector; and
determine the output peak detector value by subtracting the output peak detector offset from the output peak detector value of the output peak detector.

13. The system of claim 12 , further comprising an analog to digital converter in communication with each of the input peak detector and the output peak detector, the control hardware further configured to measure the input peak detector value and output peak detector value with the analog to digital converter.

14. The system of claim 12 , wherein the control hardware is further configured to adjust the precision variable gain adjuster to confirm that the output peak detector value matches the selected target level within a threshold tolerance.

Assignees

• Google Inc
• Google Llc

Inventors

• Feldman Arnold
• Mossawir Benjamin Joseph

Classifications

• H01Q3/34

  by electrical means (active lenses or reflecting arrays H01Q3/46) · CPC title

• H03G3/00

  Gain control in amplifiers or frequency changers · CPC title

• H03G3/301

  the gain being continuously variable · CPC title

• H04B17/14 Primary

  of the whole transmission and reception path, e.g. self-test loop-back · CPC title

• H03K5/1532

  Peak detectors (measuring characteristics of individual pulses G01R29/02) · CPC title