Semiconductor device and electronic device including analog/digital converter

Patent metadata

Field	Value
Publication number	US-9871526-B2
Application number	US-98406111-A
Country	US
Kind code	B2
Filing date	Jan 4, 2011
Priority date	Jan 15, 2010
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

Noise in a semiconductor device including a photo sensor is reduced. The semiconductor device includes an analog/digital converter and a photo sensor including a photodiode. The analog/digital converter includes an oscillation circuit and a counter circuit. A first signal output from the photo sensor is input to the oscillation circuit. The oscillation circuit has a function of outputting a second signal obtained by a change in oscillation frequency of the first signal. The counter circuit has a count function by which addition or subtraction is performed by a control signal with the second signal used as a clock signal. The counter circuit performs subtraction during the reset operation of the photo sensor. The counter circuit performs addition during the selection operation of the photo sensor. Thus, the output value of the analog/digital converter can be corrected.

First claim

The invention claimed is:

1. A semiconductor device comprising:
an analog/digital converter including an oscillation circuit and a counter circuit, wherein the counter circuit is configured to perform addition or subtraction of a count value in the counter circuit;
a photo sensor electrically connected to the oscillation circuit, to input a first signal to the oscillation circuit; and
a signal line electrically connected to the counter circuit, the signal line being arranged so as to select one of a state in which the counter circuit performs the addition of the count value and a state in which the counter circuit performs the subtraction of the count value,
wherein the oscillation circuit is configured to output a second signal obtained by converting the first signal to the counter circuit, the second signal having an oscillation frequency in accordance with the first signal,
wherein the counter circuit is configured to perform the addition of the count value by using the second signal as a clock signal or perform the subtraction of the count value by using the second signal as a clock signal,
wherein the photo sensor includes a photodiode and a transistor,
wherein the photodiode is a pin photodiode,
wherein the transistor includes a region overlapping with a p-type layer of the photodiode or an n-type layer of the photodiode through an insulating film, and
wherein an i-type layer of the photodiode includes a region not overlapping with the transistor.

2. The semiconductor device according to claim 1 ,
wherein the pin photodiode includes silicon.

3. The semiconductor device according to claim 1 ,
wherein the counter circuit is configured to correct an output value by performing the addition of the count value when the photo sensor is in a second state and by performing the subtraction of the count value when the photo sensor is in a first state.

4. The semiconductor device according to claim 1 ,
wherein the first signal is an analog signal, and
wherein the second signal is a digital signal.

5. The semiconductor device according to claim 1 , further comprising:
a readout circuit, the readout circuit including:
a transistor; and
a capacitor electrically connected to the transistor,

wherein a wiring is electrically connected to the transistor and the capacitor.

6. The semiconductor device according to claim 1 ,
wherein every time the second signal of the oscillation circuit is changed between a first potential higher than a certain potential and a second potential lower than the certain potential, the count value is decreased by one.

7. A semiconductor device comprising:
an analog/digital converter including an oscillation circuit and a counter circuit, wherein the counter circuit is configured to perform addition or subtraction of a count value in the counter circuit;
a photo sensor including a photodiode, a first transistor, and a second transistor; and
a signal line electrically connected to the counter circuit, the signal line being arranged so as to select one of a state in which the counter circuit performs the addition of the count value and a state in which the counter circuit performs the subtraction of the count value,
wherein a first terminal of the photodiode is electrically connected to a first wiring,
wherein a second terminal of the photodiode is electrically connected to a gate of the first transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a second wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring configured to output a first signal,
wherein a gate of the second transistor is electrically connected to a fourth wiring,
wherein the oscillation circuit is configured to output a second signal obtained by converting the first signal to the counter circuit, the second signal having an oscillation frequency in accordance with the first signal,
wherein the counter circuit is configured to perform the addition of the count value by using the second signal as a clock signal or perform the subtraction of the count value by using the second signal as a clock signal,
wherein the photodiode is a pin photodiode,
wherein the second transistor includes a region overlapping with a p-type layer of the photodiode or an n-type layer of the photodiode through an insulating film, and
wherein an i-type layer of the photodiode includes a region not overlapping with the second transistor.

8. The semiconductor device according to claim 7 , further comprising a third transistor between the second terminal of the photodiode and the gate of the first transistor,
wherein one of a source and a drain of the third transistor is electrically connected to the second terminal of the photodiode,
wherein the other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor, and
wherein a gate of the third transistor is electrically connected to a fifth wiring.

9. The semiconductor device according to claim 8 ,
wherein the first transistor and the second transistor include a channel formation region including crystalline silicon, and
wherein the third transistor includes a channel formation region including oxide semiconductor.

10. The semiconductor device according to claim 9 , wherein the channel formation region has a carrier concentration lower than 1×10 14 /cm 3 .

11. The semiconductor device according to claim 7 , wherein at least one of the first transistor and the second transistor includes a channel formation region including oxide semiconductor.

12. The semiconductor device according to claim 7 , wherein the pin photodiode includes silicon.

13. The semiconductor device according to claim 7 ,
wherein the counter circuit is configured to correct an output value by performing the addition of the count value when the photo sensor is in a second state and by performing the subtraction of the count value when the photo sensor is in a first state.

14. The semiconductor device according to claim 7 ,
wherein the first signal is an analog signal, and
wherein the second signal is a digital signal.

15. The semiconductor device according to claim 7 ,
wherein the photodiode includes a first region having n-type conductivity and a second region having a p-type conductivity, and
wherein the gate of the second transistor overlaps with one of the first region and the second region.

16. The semiconductor device according to claim 7 ,
wherein the photodiode includes a first region having n-type conductivity and a second region having a p-type conductivity, and
wherein the first region and the second region are over and in contact with a same surface.

17. The semiconductor device according to claim 7 , further comprising:
a readout circuit, the readout circuit including:
a third transistor; and
a capacitor electrically connected to the third transistor,

wherein the third wiring is electrically connected to the third transistor and the capacitor.

18. The semiconductor device according to claim 7 ,
wherein every time the second signal of the oscillation circuit is changed between a first potential higher than a certain potential and a second potential lower than the certain potential, the count value is decreased by one.

19. A semiconductor device comprising:
an ana

Assignees

• Kurokawa Yoshiyuki
• Semiconductor Energy Lab

Inventors

• Kurokawa Yoshiyuki

Classifications

• H04N25/76

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title

• H04N25/60

  Noise processing, e.g. detecting, correcting, reducing or removing noise · CPC title

• H03M1/123

  Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters · CPC title

• H04N5/374

  Electricity · mapped topic

• H03M1/60

  with intermediate conversion to frequency of pulses · CPC title