Methods and apparatus for counting pulses representing an analog signal

Patent metadata

Field	Value
Publication number	US-9768785-B2
Application number	US-201514850067-A
Country	US
Kind code	B2
Filing date	Sep 10, 2015
Priority date	Jul 1, 2011
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

Digital focal plane arrays (DFPAs) with multiple counters per unit cell can be used to convert analog signals to digital data and to filter the digital data. Exemplary DFPAs include two-dimensional arrays of unit cells, where each unit cell is coupled to a corresponding photodetector in a photodetector array. Each unit cell converts photocurrent from its photodetector to a digital pulse train that is coupled to multiple counters in the unit cell. Each counter in each unit cell can be independently controlled to filter the pulse train by counting up or down and/or by transferring data as desired. For example, a unit cell may perform in-phase/quadrature filtering of homodyne- or heterodyne-detected photocurrent with two counters: a first counter toggled between increment and decrement modes with an in-phase signal and a second counter toggled between increment and decrement modes with a quadrature signal.

First claim

The invention claimed is:

1. An apparatus for counting pulses representing an analog signal, the apparatus comprising:
an integrated circuit operably coupled to a photodetector array, the integrated circuit comprising a plurality of unit cells, wherein at least one unit cell in the plurality of unit cells comprises:
(i) a converter to convert a photocurrent from at least one photodetector in the photodetector array to a series of pulses;
(ii) a first counter, operably coupled to the converter, to count first pulses in the series of pulses in response to a first clock selection signal and according to a first operating mode; and
(iii) a second counter, operably coupled to the converter, to count second pulses in the series of pulses in response to a second clock selection signal and according to a second operating mode,
wherein the first operating mode and the second operating mode are independently controllable by a first control signal and a second control signal, respectively.

2. The apparatus of claim 1 , wherein the at least one unit cell further comprises a switch, wherein the converter is electrically coupled to the first counter and the second counter via the switch.

3. The apparatus of claim 1 , wherein the at least one unit cell further comprises a multiplexer, wherein the converter is electrically coupled to the first counter and the second counter via the multiplexer.

4. The apparatus of claim 1 , wherein an integration time of the first counter differs from an integration time of the second counter.

5. The apparatus of claim 1 , wherein the integrated circuit further comprises intra-cell transfer circuitry to shift data between the first counter and the second counter.

6. The apparatus of claim 5 , wherein the first counter is configured to shift data to the second counter in response to a shift signal.

7. The apparatus of claim 1 , wherein the first counter and/or the second counter is/are a partitioned segment of a segmented counter.

8. The apparatus of claim 1 , wherein:
the first operating mode is switchable, by the first control signal, to at least one of: a barrel shift mode, a right shift mode, a left shift mode, a ripple count mode, a ones complement mode, a count-up mode, a count-down mode, a data shift mode, or a read-out mode; and
the second operating mode is switchable, by the second control signal, to at least one of: a barrel shift mode, a right shift mode, a left shift mode, a ripple count mode, a ones complement mode, a count-up mode, a count-down mode, a data shift mode, or a read-out mode.

9. The apparatus of claim 1 , wherein the at least one unit cell further comprises logic circuitry, operably coupled to at least one of the first counter and the second counter, to convert a count stored in the first counter into an absolute value of the count.

10. The apparatus of claim 1 , wherein the first counter is configured to perform a multiply-by-two operation.

11. The apparatus of claim 1 , wherein the first counter is configured to perform a divide-by-two operation.

12. A method of counting pulses representing an analog signal in at least one unit cell in a plurality of unit cells, the at least one unit cell comprising a first counter, a second counter, and a converter operably coupled to the first counter, the second counter, and a photodetector array, the method comprising:
producing a photocurrent, with at least one photodetector in the photodetector array, in response to detection of light;
converting the photocurrent, with the converter, into a series of pulses;
counting, with the first counter, first pulses in the series of pulses according to a first operating mode set by a first control signal; and
counting, with the second counter, second pulses in the series of pulses according to a second operating mode set by a second control signal that is different from the first control signal.

13. The method of claim 12 , further comprising:
shifting at least a portion of a count of the first counter and at least a portion of a count of the second counter to different respective unit cells in the plurality of unit cells;
receiving shifted counts in each of the first counter and the second counter from further different respective unit cells in the plurality of unit cells; and
counting: (1) third pulses in the series of pulses with the first counter and (2) fourth pulses in the series of pulses with the second counter, to obtain further respective counts.

14. The method of claim 12 , wherein the first counter and the second counter are independently controllable by the first control signal and the second control signal, respectively.

15. The method of claim 12 , further comprising:
shifting data from the first counter to the second counter and/or shifting data from the second counter to the first counter in response to a shift signal.

16. The method of claim 12 , wherein:
the first operating mode is one of: a barrel shift mode, a right shift mode, a left shift mode, a ripple count mode, a ones complement mode, a count-up mode, a count-down mode, a data shift mode, or a read-out mode; and/or
the second operating mode is one of: a barrel shift mode, a right shift mode, a left shift mode, a ripple count mode, a ones complement mode, a count-up mode, a count-down mode, a data shift mode, or a read-out mode.

17. The method of claim 12 , further comprising:
switching the first operating mode, by the first control signal, to one of: a barrel shift mode, a right shift mode, a left shift mode, a ripple count mode, a ones complement mode, a count-up mode, a count-down mode, a data shift mode, or a read-out mode; and/or
switching the second operating mode, by the second control signal, to one of: a barrel shift mode, a right shift mode, a left shift mode, a ripple count mode, a ones complement mode, a count-up mode, a count-down mode, a data shift mode, or a read-out mode.

18. The method of claim 12 , further comprising:
converting a count stored in the first counter into an absolute value of the count.

19. The method of claim 12 , further comprising:
performing a multiply-by-two operation in at least one of the first counter and the second counter.

20. The method of claim 12 , further comprising:
performing a divide-by-two operation in at least one of the first counter and the second counter.

Assignees

• Massachusetts Inst Technology

Inventors

• Schultz Kenneth I
• Tyrrell Brian
• Kelly Michael W
• Colonero Curtis B
• Candell Lawrence M
• Mooney Daniel

Classifications

• H03M1/60

  with intermediate conversion to frequency of pulses · CPC title

• H03M1/004

  Reconfigurable analogue/digital or digital/analogue converters (H03M1/02 takes precedence) · CPC title

• H03K23/548

  Reversible counters · CPC title

• H03K21/023 Primary

  comprising pulse shaping or differentiating circuits · CPC title

• G11C19/00

  Digital stores in which the information is moved stepwise, e.g. shift registers · CPC title