Memory device and memory system including the same, and operation method of memory device

Patent metadata

Field	Value
Publication number	US-9576629-B2
Application number	US-201314030697-A
Country	US
Kind code	B2
Filing date	Sep 18, 2013
Priority date	Apr 17, 2013
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

A memory device includes a memory cell array having a plurality of memory cells, a storage unit suitable for storing a fail address corresponding to a fail memory cell in the memory cell array, an available storage capacity determination unit suitable for generating available capacity information indicating an available storage capacity in the storage unit, and an output circuit suitable for outputting the available capacity information.

First claim

What is claimed is:

1. A memory device comprising:
a memory cell array having a plurality of memory cells;
a storage unit suitable for storing a fail address corresponding to a fail memory cell in the memory cell array;
an available storage capacity determination unit suitable for generating available capacity information indicating an available storage capacity in the storage unit;
an output circuit suitable for outputting the available capacity information; and
a command decoder suitable for generating an active command, a precharge command, a read command and a write command by decoding command signals inputted to the memory device in a normal mode, and generating a repair active command for indicating that an additional fail address is inputted to the memory device and a repair write command for writing the additional fail address to the storage unit in a repairable mode,
wherein the additional fail address is stored temporarily in the memory device in response to the repair active command, and the temporarily stored additional fail address is programmed to the storage unit in response to the repair writing command.

2. The memory device of claim 1 , wherein a boot-up operation for transmitting all of the respective fail addresses stored in the storage unit to a register unit is performed in an initial operation of the memory device.

3. The memory device of claim 1 , wherein the storage unit includes any one of an e-fuse array, a NAND flash memory, a NOR flash memory, a magnetic random access memory, a spin transfer magnetic random access memory, a resistive random access memory, and a phase change random access memory.

4. The memory device of claim 1 , wherein the storage unit includes a plurality of storage sets, each storing respective validity information and a respective fail address, and
wherein the available storage capacity determination unit includes:
a counter suitable for counting the number of activated validity information and generating occupied amount information; and
an available capacity information generator suitable for generating the available capacity information by subtracting the occupied amount information from the total number of the storage sets in the storage unit.

5. The memory device of claim 4 , wherein the counter counts the number of activated validity information when the boot-up operation is performed.

6. A memory device comprising:
a memory cell array having a plurality of memory cells;
a storage unit suitable for storing a fail address corresponding to a fail memory cell within the memory cell array;
an available storage capacity determination unit suitable for generating occupied amount information indicating a storage capacity occupied in the storage unit; and
a control unit suitable for controlling the storage unit to be stored with an additional fail address inputted from the outside at an available position of the storage unit determined using the occupied amount information; and
a command decoder suitable for generating an active command, a precharge command, a read command and a write command by decoding command signals inputted to the memory device in a normal mode, and generating a repair active command for indicating that an additional fail address is inputted to the memory device and a repair write command for writing the additional fail address to the storage unit in a repairable mode,
wherein the additional fail address is stored temporarily in the control unit in response to the repair active command, and the temporarily stored additional address is programmed to the storage unit in response to the repair writing command.

7. The memory device of claim 6 , further comprising an output circuit suitable for outputting the available capacity information.

8. The memory device of claim 6 , wherein a boot-up operation for transmitting all of the respective fail addresses stored in the storage unit to a register unit is performed in an initial operation of the memory device.

9. The memory device of claim 8 , wherein the available storage capacity determination unit includes:
a counter suitable for counting the number of activated validity information and generating occupied amount information; and
an available capacity information generator suitable for generating the available capacity information by subtracting the occupied amount information from the total number of the storage sets in the storage unit.

10. The memory device of claim 6 , wherein the storage unit includes any one of an e-fuse array, a NAND flash memory, a NOR flash memory, a magnetic random access memory, a spin transfer magnetic random access memory, a resistive random access memory, and a phase change random access memory.

11. The memory device of claim 6 , wherein the available storage capacity determination unit generates available capacity information indicating a storage capacity available in the storage unit.

12. The memory device of claim 6 , wherein the storage unit includes a plurality of storage sets, each storing respective validity information and a respective fail address.

13. An operation method of a memory system including a memory device and a memory controller, the method comprising:
initializing the memory device and generating an available capacity information indicating remaining storage capacity of a storage unit of the memory device;
transmitting the available capacity information from the memory device to the memory controller;
determining whether to perform a repair operation based on the available capacity information;
controlling the memory device to enter into a repairable mode by the memory controller, when it's determined to perform the repair operation;
transmitting an additional fail address and a repair active command from the memory controller to the memory device;
temporarily storing the additional fail address in response to the repair active command;
transmitting a repair write command from the memory controller to the memory device;
programming the temporarily stored additional address to the storage unit in response to the repair write command; and
controlling the memory device to exit the repairable mode by the memory controller.

Assignees

• Sk Hynix Inc

Inventors

• Song Choung-Ki

Classifications

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G11C2029/0401

  in embedded memories · CPC title

• G11C7/20

  Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory · CPC title

• G11C29/785

  with redundancy programming schemes · CPC title

• G11C7/24 Primary

  Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells · CPC title